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PIC16F917/916/914/913 Data Sheet
28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
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Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS41250E-page ii
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology
High-Performance RISC CPU:
* Only 35 instructions to learn: - All single-cycle instructions except branches * Operating speed: - DC - 20 MHz oscillator/clock input - DC - 200 ns instruction cycle * Program Memory Read (PMR) capability * Interrupt capability * 8-level deep hardware stack * Direct, Indirect and Relative Addressing modes
Low-Power Features:
* Standby Current: - <100 nA @ 2.0V, typical * Operating Current: - 8.5 A @ 32 kHz, 2.0V, typical - 100 A @ 1 MHz, 2.0V, typical * Watchdog Timer Current: - 1 A @ 2.0V, typical
Peripheral Features:
* Liquid Crystal Display module: - Up to 60 pixel drive capability on 28-pin devices - Up to 96 pixel drive capability on 40-pin devices - Four commons * Up to 35 I/O pins and 1 input-only pin: - High-current source/sink for direct LED drive - Interrupt-on-pin change - Individually programmable weak pull-ups * In-Circuit Serial ProgrammingTM (ICSPTM) via two pins * Analog comparator module with: - Two analog comparators - Programmable on-chip voltage reference (CVREF) module (% of VDD) - Comparator inputs and outputs externally accessible * A/D Converter: - 10-bit resolution and up to 8 channels * Timer0: 8-bit timer/counter with 8-bit programmable prescaler * Enhanced Timer1: - 16-bit timer/counter with prescaler - External Gate Input mode - Option to use OSC1 and OSC2 as Timer1 oscillator if INTOSCIO or LP mode is selected * Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler * Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) * Up to 2 Capture, Compare, PWM modules: - 16-bit Capture, max. resolution 12.5 ns - 16-bit Compare, max. resolution 200 ns - 10-bit PWM, max. frequency 20 kHz * Synchronous Serial Port (SSP) with I2CTM
Special Microcontroller Features:
* Precision Internal Oscillator: - Factory calibrated to 1% - Software selectable frequency range of 8 MHz to 32 kHz - Software tunable - Two-Speed Start-up mode - Crystal fail detect for critical applications - Clock mode switching during operation for power savings * Power-saving Sleep mode * Wide operating voltage range (2.0V-5.5V) * Industrial and Extended temperature range * Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Brown-out Reset (BOR) with software control option * Enhanced Low-Current Watchdog Timer (WDT) with on-chip oscillator (software selectable nominal 268 seconds with full prescaler) with software enable * Multiplexed Master Clear with pull-up/input pin * Programmable code protection * High-Endurance Flash/EEPROM cell: - 100,000 write Flash endurance - 1,000,000 write EEPROM endurance - Flash/Data EEPROM retention: > 40 years
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 1
PIC16F917/916/914/913
Program Memory Device Flash (words/bytes) PIC16F913 PIC16F914 PIC16F916 PIC16F917 4K/7K 4K/7K 8K/14K 8K/14K SRAM (bytes) 256 256 352 352 EEPROM (bytes) 256 256 256 256 24 35 24 35 Data Memory I/O 10-bit A/D (ch) 5 8 5 8 LCD (segment drivers) 16 24 16 24 Timers 8/16bit 2/1 2/1 2/1 2/1
CCP
1 2 1 2
Pin Diagrams - PIC16F914/917, 40-Pin
40-pin PDIP
RE3/MCLR/VPP RA0/AN0/C1-/SEG12 RA1/AN1/C2-/SEG7 RA2/AN2/C2+/VREF-/COM2 RA3/AN3/C1+/VREF+/SEG15 RA4/C1OUT/T0CKI/SEG4 RA5/AN4/C2OUT/SS/SEG5 RE0/AN5/SEG21 RE1/AN6/SEG22 RE2/AN7/SEG23 VDD VSS RA7/OSC1/CLKI/T1OSI RA6/OSC2/CLKO/T1OSO RC0/VLCD1 RC1/VLCD2 RC2/VLCD3 RC3/SEG6 RD0/COM3 RD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/ICSPDAT/ICDDAT/SEG13 RB6/ICSPCLK/ICDCK/SEG14 RB5/COM1 RB4/COM0 RB3/SEG3 RB2/SEG2 RB1/SEG1 RB0/INT/SEG0 VDD VSS RD7/SEG20 RD6/SEG19 RD5/SEG18 RD4/SEG17 RC7/RX/DT/SDI/SDA/SEG8 RC6/TX/CK/SCK/SCL/SEG9 RC5/T1CKI/CCP1/SEG10 RC4/T1G/SDO/SEG11 RD3/SEG16 RD2/CCP2
DS41250E-page 2
Preliminary
PIC16F914/917
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
Pin Diagrams - PIC16F913/916, 28-Pin
28-pin PDIP, SOIC, SSOP
RE3/MCLR/VPP RA0/AN0/C1-/SEG12 RA1/AN1/C2-/SEG7 RA2/AN2/C2+/VREF-/COM2 RA3/AN3/C1+/VREF+/COM3/SEG15 RA4/C1OUT/T0CKI/SEG4 RA5/AN4/C2OUT/SS/SEG5 VSS RA7/OSC1/CLKI/T1OSI RA6/OSC2/CLKO/T1OSO RC0/VLCD1 RC1/VLCD2 RC2/VLCD3 RC3/SEG6
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
RB7/ICSPDAT/ICDDAT/SEG13 RB6/ICSPCLK/ICDCK/SEG14 RB5/COM1 RB4/COM0 RB3/SEG3 RB2/SEG2 RB1/SEG1 RB0/INT/SEG0 VDD VSS RC7/RX/DT/SDI/SDA/SEG8 RC6/TX/CK/SCK/SCL/SEG9 RC5/T1CKI/CCP1/SEG10 RC4/T1G/SDO/SEG11
RB7/ICSPDAT/ICDDAT/SEG13
RB6/ICSPCLK/ICDCK/SEG14
28-pin QFN
RA0/AN0/C1-/SEG12
RA1/AN1/C2-/SEG7
RE3/MCLR/VPP
PIC16F913/916 RB5/COM1
28 27
26 25 24 23
22
RB4/COM0
RA2/AN2/C2+/VREF-/COM2 RA3/AN3/C1+/VREF+/COM3/SEG15 RA4/C1OUT/T0CKI/SEG4 RA5/AN4/C2OUT/SS/SEG5 VSS RA7/OSC1/CLKI/T1OSI RA6/OSC2/CLKO/T1OSO
1 2 3 4 5 6 7 8 9
21 20 19 PIC16F913/916 18 17 16 15
RB3/SEG3 RB2/SEG2 RB1/SEG1 RB0/INT/SEG0 VDD VSS RC7/RX/DT/SDI/SDA/SEG8
10
11
12 RC4/T1G/SDO/SEG11
13 RC5/T1CKI/CCP1/SEG10
(c) 2005 Microchip Technology Inc.
Preliminary
RC6/TX/CK/SCK/SCL/SEG9
RC0/VLCD1
RC1/VLCD2
RC2/VLCD3
RC3/SEG6
14
DS41250E-page 3
PIC16F917/916/914/913
Pin Diagrams - PIC16F914/917, 44-Pin
RC6/TX/CK/SCK/SCL/SEG9 RC5/T1CKI/CCP1/SEG10 RC4/T1G/SDO/SEG11 RD3/SEG16 RD2/CCP2 RD1 RD0/COM3 RC3/SEG6 RC2/VLCD3 RC1/VLCD2 NC 44 43 42 41 40 39 38 37 36 35 34
44-pin TQFP
NC NC RB4/COM0 RB5/COM1 RB6/ICSPCLK/ICDCK/SEG14 RB7/ICSPDAT/ICDDAT/SEG13 RE3/MCLR/VPP RA0/C1-/AN0/SEG12 RA1/C2-/AN1/SEG7 RA2/AN2/C2+/VREF-/COM2 RA3/AN3/VREF+/C1+/SEG15
12 13 14 15 16 17 18 19 20 21 22
RC7/RX/DT/SDI/SDA/SEG8 RD4/SEG17 RD5/SEG18 RD6/SEG19 RD7/SEG20 VSS VDD RB0/SEG0/INT RB1/SEG1 RB2/SEG2 RB3/SEG3
1 2 3 4 5 6 7 8 9 10 11
PIC16F914/917
33 32 31 30 29 28 27 26 25 24 23
NC RC0/VLCD1 RA6/OSC2/CLKO/T1OSO RA7/OSC1/CLKI/T1OSI VSS VDD RE2/AN7/SEG23 RE1/AN6/SEG22 RE0/AN5/SEG21 RA5/AN4/C2OUT/SS/SEG5 RA4/C1OUT/T0CKI/SEG4
44-pin QFN
44 43 42 41 40 39 38 37 36 35 34
RC6/TX/CK/SCK/SCL/SEG9 RC5/T1CKI/CCP1/SEG10 RC4/T1G/SDO/SEG11 RD3/SEG16 RD2/CCP2 RD1 RD0/COM3 RC3/SEG6 RC2/VLCD3 RC1/VLCD2 RC0/VLDC1
DS41250E-page 4
Preliminary
RB3/SEG3 NC RB4/COM0 RB5/COM1 RB6/ICSPCLK/ICDCK/SEG14 RB7/ICSPDAT/ICDDAT/SEG13 RE3/MCLR/VPP RA0/AN0/C1-/SEG12 RA1/AN1/C2-/SEG7 RA2/AN2/C2+/VREF-/COM2 RA3/AN3/C1+/VREF+/SEG15
12 13 14 15 16 17 18 19 20 21 22
RC7/RX/DT/SDI/SDA/SEG8 RD4/SEG17 RD5/SEG18 RD6/SEG19 RD7/SEG20 VSS VDD VDD RB0/INT/SEG0 RB1/SEG1 RB2/SEG2
1 2 3 4 5 6 7 8 9 10 11
PIC16F914/917
33 32 31 30 29 28 27 26 25 24 23
RA6/OSC2/CLK0/T1OSO RA7/OSC1/CLKI/T1OSI VSS VSS NC VDD RE2/AN7/SEG23 RE1/AN6/SEG22 RE0/AN5/SEG21 RA5/AN4/C2OUT/SS/SEG5 RA4/C1OUT/T0CKI/SEG4
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Memory Organization ................................................................................................................................................................. 13 3.0 I/O Ports ..................................................................................................................................................................................... 31 4.0 Clock Sources ............................................................................................................................................................................ 69 5.0 Timer0 Module ........................................................................................................................................................................... 81 6.0 Timer1 Module With Gate Control.............................................................................................................................................. 85 7.0 Timer2 Module ........................................................................................................................................................................... 90 8.0 Comparator Module.................................................................................................................................................................... 93 9.0 Liquid Crystal Display (LCD) Driver Module............................................................................................................................. 101 10.0 Programmable Low-Voltage Detect (PLVD) Module................................................................................................................ 125 11.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).............................................................. 127 12.0 Analog-to-Digital Converter (A/D) Module................................................................................................................................ 143 13.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 153 14.0 SSP Module Overview ............................................................................................................................................................. 159 15.0 Capture/Compare/PWM Modules ............................................................................................................................................ 177 16.0 Special Features of the CPU.................................................................................................................................................... 185 17.0 Instruction Set Summary .......................................................................................................................................................... 205 18.0 Development Support............................................................................................................................................................... 215 19.0 Electrical Specifications............................................................................................................................................................ 219 20.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 245 21.0 Packaging Information.............................................................................................................................................................. 247 Appendix A: Data Sheet Revision History.......................................................................................................................................... 257 Appendix B: Migrating From Other PICmicro(R) Devices..................................................................................................................... 257 Appendix C: Conversion Considerations ........................................................................................................................................... 258 Index .................................................................................................................................................................................................. 259 On-line Support .................................................................................................................................................................................. 267 Systems Information and Upgrade Hot Line ...................................................................................................................................... 267 Reader Response .............................................................................................................................................................................. 268 Product Identification System ............................................................................................................................................................ 269
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Most Current Data Sheet
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 5
PIC16F917/916/914/913
NOTES:
DS41250E-page 6
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
1.0 DEVICE OVERVIEW
This document contains device specific information for the PIC16F91X. Additional information may be found in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023), downloaded from the Microchip web site. The Reference Manual should be considered a complementary document to this data sheet and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. The PIC16F91X devices are covered by this data sheet. It is available in 28/40/44-pin packages. Figure 1-1 shows a block diagram of the PIC16F913/ 916 device and Table 1-1 shows the pinout description. Figure 1-2 shows a block diagram of the PIC16F914/ 917 device and Table 1-1 shows the pinout description.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 7
PIC16F917/916/914/913
FIGURE 1-1: PIC16F913/916 BLOCK DIAGRAM
INT Configuration 13 Program Counter Flash 4k/8k x 14 Program Memory 8-Level Stack (13-bit) RAM 256/352 bytes File Registers RAM Addr 9 Addr MUX Instruction Reg Direct Addr 7 8 Indirect Addr PORTB RB0/INT/SEG0 RB1/SEG1 RB2/SEG2 RB3/SEG3 RB4/COM0 RB5/COM1 RB6/ICSPCLK/ICDCK/SEG14 RB7/ICSPDAT/ICDDAT/SEG13 PORTC 3
Power-up Timer
Data Bus
8
PORTA RA0/AN0/C1-/SEG12 RA1/AN1/C2-/SEG7 RA2/AN2/C2+/VREF-/COM2 RA3/AN3/C1+/VREF+/COM3/SEG15 RA4/C1OUT/T0CKI/SEG4 RA5/AN4/C2OUT/SS/SEG5 RA6/OSC2/CLKO/T1OSO RA7/OSC1/CLKI/T1OSI
Program 14 Bus
Program Memory Read (PRM)
FSR Reg Status Reg 8
MUX
Instruction Decode and Control OSC1/CLKI OSC2/CLKO Timing Generation
Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
ALU 8 W Reg PORTE
RC0/VLCD1 RC1/VLCD2 RC2/VLCD3 RC3/SEG6 RC4/T1G/SDO/SEG11 RC5/T1CKI/CCP1/SEG10 RC6/TX/CK/SCK/SCL/SEG9 RC7/RX/DT/SDI/SDA/SEG8
Internal Oscillator Block VDD VSS
RE3/MCLR/VPP
Data EEPROM 256 bytes Timer0 Timer1 Timer2 10-bit A/D
Comparators
CCP1
SSP
Addressable USART
BOR
PLVD
LCD
DS41250E-page 8
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
FIGURE 1-2: PIC16F914/917 BLOCK DIAGRAM
INT Configuration 13 Program Counter Flash 4k/8k x 14 Program Memory 8-Level Stack (13-bit) RAM 256/352 bytes File Registers RAM Addr 9 Addr MUX Instruction Reg Direct Addr 7 8 Indirect Addr PORTB RB0/INT/SEG0 RB1/SEG1 RB2/SEG2 RB3/SEG3 RB4/COM0 RB5/COM1 RB6/ICSPCLK/ICDCK/SEG14 RB7/ICSPDAT/ICDDAT/SEG13 PORTC 3
Power-up Timer
Data Bus
8
PORTA RA0/AN0/C1-/SEG12 RA1/AN1/C2-/SEG7 RA2/AN2/C2+/VREF-/COM2 RA3/AN3/C1+/VREF+/SEG15 RA4/C1OUT/T0CKI/SEG4 RA5/AN4/C2OUT/SS/SEG5 RA6/OSC2/CLKO/T1OSO RA7/OSC1/CLKI/T1OSI
Program 14 Bus
Program Memory Read (PRM)
FSR Reg Status Reg 8
MUX
Instruction Decode and Control OSC1/CLKI OSC2/CLKO Timing Generation
Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
ALU 8 W Reg PORTD
RC0/VLCD1 RC1/VLCD2 RC2/VLCD3 RC3/SEG6 RC4/T1G/SDO/SEG11 RC5/T1CKI/CCP1/SEG10 RC6/TX/CK/SCK/SCL/SEG9 RC7/RX/DT/SDI/SDA/SEG8
Internal Oscillator Block VDD VSS PORTE
RD0/COM3 RD1 RD2/CCP2 RD3/SEG16 RD4/SEG17 RD5/SEG18 RD6/SEG19 RD7/SEG20
RE0/AN5/SEG21 RE1/AN6/SEG22 RE2/AN7/SEG23 RE3/MCLR/VPP
Timer0
Timer1
Timer2
10-bit A/D
Data EEPROM 256 bytes
Comparators
CCP1
CCP2
SSP
Addressable USART
BOR
PLVD
LCD
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 9
PIC16F917/916/914/913
TABLE 1-1: PIC16F91X PINOUT DESCRIPTIONS
Function
RA0 AN0 C1SEG12 RA1/AN1/C2-/SEG7 RA1 AN1 C2SEG7 RA2/AN2/C2+/VREF-/COM2 RA2 AN2 C2+ VREFCOM2 RA3/AN3/C1+/VREF+/COM3 SEG15
(1)/
Name
RA0/AN0/C1-/SEG12
Input Output Type Type
TTL AN -- -- TTL AN -- -- TTL AN -- AN -- TTL AN -- AN -- -- TTL -- ST -- TTL AN -- TTL -- TTL -- -- -- TTL XTAL ST XTAL TTL ST -- TTL -- CMOS General purpose I/O. -- AN AN -- AN AN -- AN -- AN -- AN -- AN AN
Description
Analog input Channel 0/Comparator 1 input - negative. Comparator 1 negative input. LCD analog output. Analog input Channel 1/Comparator 2 input - negative. Comparator 2 negative input. LCD analog output. Analog input Channel 2/Comparator 2 input - positive. Comparator 2 positive input. External Voltage Reference - negative. LCD analog output. Analog input Channel 3/Comparator 1 input - positive. Comparator 1 positive input. External Voltage Reference - positive. LCD analog output. LCD analog output.
CMOS General purpose I/O.
CMOS General purpose I/O.
RA3 AN3 C1+ VREF+ COM3(1) SEG15
CMOS General purpose I/O.
RA4/C1OUT/T0CKI/SEG4
RA4 C1OUT T0CKI SEG4
CMOS General purpose I/O. CMOS Comparator 1 output. -- AN -- -- AN XTAL XTAL -- -- -- -- AN AN Timer0 clock input. LCD analog output. Analog input Channel 4. Slave select input. LCD analog output. Crystal/Resonator. Timer1 oscillator output. Crystal/Resonator. Clock input. Timer1 oscillator input. External interrupt pin. LCD analog output. LCD analog output.
RA5/AN4/C2OUT/SS/SEG5
RA5 AN4 C2OUT SS SEG5
CMOS General purpose I/O. CMOS Comparator 2 output.
RA6/OSC2/CLKO/T1OSO
RA6 OSC2 CLKO T1OSO
CMOS General purpose I/O. CMOS TOSC/4 reference clock. CMOS General purpose I/O.
RA7/OSC1/CLKI/T1OSI
RA7 OSC1 CLKI T1OSI
RB0/INT/SEG0
RB0 INT SEG0
CMOS General purpose I/O. Individually enabled pull-up.
RB1/SEG1 Legend:
RB1 SEG1 AN = Analog input or output TTL = TTL compatible input HV = High Voltage
CMOS General purpose I/O. Individually enabled pull-up.
CMOS = CMOS compatible input or output D = Direct ST = Schmitt Trigger input with CMOS levels XTAL = Crystal
Note 1: 2:
COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917. Pins available on PIC16F914/917 only.
DS41250E-page 10
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
TABLE 1-1: PIC16F91X PINOUT DESCRIPTIONS (CONTINUED)
Function
RB2 SEG2 RB3/SEG3 RB4/COM0 RB3 SEG3 RB4 COM0 RB5/COM1 RB5 COM1 RB6/ICSPCLK/ICDCK/SEG14 RB6 ICSPCLK ICDCK SEG14 RB7/ICSPDAT/ICDDAT/SEG13 RB7 ICSPDAT ICDDAT SEG13 RC0/VLCD1 RC1/VLCD2 RC2/VLCD3 RC3/SEG6 RC4/T1G/SDO/SEG11 RC0 VLCD1 RC1 VLCD2 RC2 VLCD3 RC3 SEG6 RC4 T1G SDO SEG11 RC5/T1CKI/CCP1/SEG10 RC5 T1CKI CCP1 SEG10 RC6/TX/CK/SCK/SCL/SEG9 RC6 TX CK SCK SCL SEG9 Legend: AN = Analog input or output TTL = TTL compatible input HV = High Voltage
Name
RB2/SEG2
Input Output Type Type
TTL -- TTL -- TTL -- TTL -- TTL ST ST -- TTL ST ST -- ST AN ST AN ST AN ST -- ST ST -- -- ST ST ST -- ST -- ST ST ST -- AN AN LCD analog output. LCD analog output.
Description
CMOS General purpose I/O. Individually enabled pull-up. CMOS General purpose I/O. Individually enabled pull-up. CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. AN LCD analog output. CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. AN LCD analog output. CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. -- -- AN ICSPTM clock. ICD clock I/O. LCD analog output.
CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. CMOS ICSP Data I/O. CMOS ICD Data I/O. AN -- -- -- AN -- AN -- AN LCD analog output. LCD analog input. LCD analog input. LCD analog input. LCD analog output. Timer1 gate input. LCD analog output. Timer1 clock input. LCD analog output. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS Serial data output. CMOS General purpose I/O. CMOS Capture 1 input/Compare 1 output/PWM 1 output. CMOS General purpose I/O. CMOS USART asynchronous serial transmit. CMOS USART synchronous serial clock. CMOS SPITM clock. CMOS I2CTM clock. AN LCD analog output.
CMOS = CMOS compatible input or output D = Direct ST = Schmitt Trigger input with CMOS levels XTAL = Crystal
Note 1: 2:
COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917. Pins available on PIC16F914/917 only.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 11
PIC16F917/916/914/913
TABLE 1-1: PIC16F91X PINOUT DESCRIPTIONS (CONTINUED)
Function
RC7 RX DT SDI SDA SEG8 RD0/COM3(1, 2) RD1
(2)
Name
RC7/RX/DT/SDI/SDA/SEG8
Input Output Type Type
ST ST ST ST ST -- ST -- ST ST ST ST -- ST -- ST -- ST -- ST -- ST AN -- ST AN -- ST AN -- ST ST HV D D CMOS General purpose I/O. --
Description
USART asynchronous serial receive.
CMOS USART synchronous serial data. CMOS SPITM data input. CMOS I2CTM data. AN AN LCD analog output. LCD analog output. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS Capture 2 input/Compare 2 output/PWM 2 output. CMOS General purpose I/O. AN AN AN AN AN -- AN -- AN -- AN -- -- -- -- -- LCD analog output. LCD analog output. LCD analog output. LCD analog output. LCD analog output. Analog input Channel 5. LCD analog output. Analog input Channel 6. LCD analog output. Analog input Channel 7. LCD analog output. Digital input only. Master Clear with internal pull-up. Programming voltage. Power supply for microcontroller. Ground reference for microcontroller. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O.
RD0 COM3 RD1 RD2 CCP2 RD3 SEG16 RD4 SEG17 RD5 SEG18 RD6 SEG19 RD7 SEG20
(2)
RD2/CCP2(2) RD3/SEG16(2) RD4/SEG17
(2)
RD5/SEG18(2) RD6/SEG19(2) RD7/SEG20
(2)
RE0/AN5/SEG21
RE0 AN5 SEG21
RE1/AN6/SEG22
(2)
RE1 AN6 SEG22
CMOS General purpose I/O.
RE2/AN7/SEG23
(2)
RE2 AN7 SEG23
CMOS General purpose I/O.
RE3/MCLR/VPP
RE3 MCLR VPP
VDD VSS Legend:
VDD VSS AN = Analog input or output TTL = TTL compatible input HV = High Voltage
CMOS = CMOS compatible input or output D = Direct ST = Schmitt Trigger input with CMOS levels XTAL = Crystal
Note 1: 2:
COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917. Pins available on PIC16F914/917 only.
DS41250E-page 12
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
2.0
2.1
MEMORY ORGANIZATION
Program Memory Organization
FIGURE 2-2:
PROGRAM MEMORY MAP AND STACK FOR THE PIC16F916/917
pc<12:0>
The PIC16F917/916/914/913 has a 13-bit program counter capable of addressing a 4k x 14 program memory space for the PIC16F913/914 (0000h-0FFFh) and an 8k x 14 program memory space for the PIC16F916/917 (0000h-1FFFh). Accessing a location above the memory boundaries for the PIC16F913 and PIC16F914 will cause a wrap around within the first 4k x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h.
CALL, RETURN RETFIE, RETLW
13
Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector 0000h
FIGURE 2-1:
PROGRAM MEMORY MAP AND STACK FOR THE PIC16F913/914
pc<12:0>
Interrupt Vector Page 0
0004h 0005h 07FFh 0800h
CALL, RETURN RETFIE, RETLW
13 On-chip Program Memory Page 1
Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector 0000h
0FFFh 1000h Page 2 17FFh 1800h Page 3 1FFFh
Interrupt Vector On-chip Program Memory Page 0
0004h 0005h 07FFh 0800h
Page 1 0FFFh 1000h
1FFFh
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 13
PIC16F917/916/914/913
2.2 Data Memory Organization
The data memory is partitioned into multiple banks which contain the General Purpose Registers (GPRs) and the Special Function Registers (SFRs). Bits RP0 and RP1 are bank select bits. RP0 RP1 (STATUS<6:5>)
= 00: Bank 0 = 01: Bank 1 = 10: Bank 2 = 11: Bank 3 Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are the General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. Some frequently used Special Function Registers from one bank are mirrored in another bank for code reduction and quicker access.
2.2.1
GENERAL PURPOSE REGISTER FILE
The register file is organized as 256 x 8 in the PIC16F913/914 and 352 x 8 in the PIC16F916/917. Each register is accessed either directly or indirectly through the File Select Register (FSR) (see Section 2.5 "Indirect Addressing, INDF and FSR Registers").
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Tables 2-1, 2-2, 2-3 and 2-4). These registers are static RAM. The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the "core" are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
DS41250E-page 14
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
FIGURE 2-3: PIC16F913/916 SPECIAL FUNCTION REGISTERS
File Address Indirect addr. (1) 80h OPTION_REG 81h PCL 82h STATUS 83h FSR 84h TRISA 85h TRISB 86h TRISC 87h 88h TRISE 89h PCLATH 8Ah INTCON 8Bh PIE1 8Ch PIE2 8Dh PCON 8Eh OSCCON 8Fh OSCTUNE 90h ANSEL 91h PR2 92h SSPADD 93h SSPSTAT 94h WPUB 95h IOCB 96h CMCON1 97h TXSTA 98h SPBRG 99h 9Ah 9Bh CMCON0 9Ch VRCON 9Dh ADRESL 9Eh ADCON1 9Fh A0h General Purpose Register 80 Bytes 96 Bytes 7Fh Bank 0 accesses 70h-7Fh Bank 1 EFh F0h FFh File Address Indirect addr. (1) 100h TMR0 101h PCL 102h STATUS 103h FSR 104h WDTCON 105h PORTB 106h LCDCON 107h LCDPS 108h LVDCON 109h PCLATH 10Ah INTCON 10Bh EEDATL 10Ch EEADRL 10Dh EEDATH 10Eh EEADRH 10Fh LCDDATA0 110h LCDDATA1 111h 112h LCDDATA3 113h LCDDATA4 114h 115h LCDDATA6 116h LCDDATA7 117h 118h LCDDATA9 119h LCDDATA10 11Ah 11Bh LCDSE0 11Ch LCDSE1 11Dh 11Eh 11Fh 120h General Purpose Register 80 Bytes accesses 70h-7Fh Bank 2 16Fh 170h 17Fh accesses 70h-7Fh Bank 3 1EFh 1F0h 1FFh File Address Indirect addr. (1) 180h OPTION_REG 181h PCL 182h STATUS 183h FSR 184h 185h TRISB 186h 187h 188h 189h PCLATH 18Ah INTCON 18Bh EECON1 18Ch EECON2(1) 18Dh 18Eh 18Fh 190h File Address Indirect addr. (1) 00h TMR0 01h PCL 02h STATUS 03h FSR 04h PORTA 05h PORTB 06h PORTC 07h 08h PORTE 09h PCLATH 0Ah INTCON 0Bh PIR1 0Ch PIR2 0Dh TMR1L 0Eh TMR1H 0Fh T1CON 10h TMR2 11h T2CON 12h SSPBUF 13h SSPCON 14h CCPR1L 15h CCPR1H 16h CCP1CON 17h RCSTA 18h TXREG 19h RCREG 1Ah 1Bh 1Ch 1Dh ADRESH 1Eh ADCON0 1Fh 20h
General Purpose Register(2) 96 Bytes
General Purpose Register
Note 1: 2:
Unimplemented data memory locations, read as `0'. Not a physical register. On the PIC16F913, unimplemented data memory locations, read as `0'.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 15
PIC16F917/916/914/913
FIGURE 2-4: PIC16F914/917 SPECIAL FUNCTION REGISTERS
File Address Indirect addr. (1) 80h OPTION_REG 81h PCL 82h STATUS 83h FSR 84h TRISA 85h TRISB 86h TRISC 87h TRISD 88h TRISE 89h PCLATH 8Ah INTCON 8Bh PIE1 8Ch PIE2 8Dh PCON 8Eh OSCCON 8Fh OSCTUNE 90h ANSEL 91h PR2 92h SSPADD 93h SSPSTAT 94h WPUB 95h IOCB 96h CMCON1 97h TXSTA 98h SPBRG 99h 9Ah 9Bh CMCON0 9Ch VRCON 9Dh ADRESL 9Eh ADCON1 9Fh A0h General Purpose Register 80 Bytes 96 Bytes 7Fh Bank 0 accesses 70h-7Fh Bank 1 EFh F0h FFh File Address Indirect addr. (1) 100h TMR0 101h PCL 102h STATUS 103h FSR 104h WDTCON 105h PORTB 106h LCDCON 107h LCDPS 108h LVDCON 109h PCLATH 10Ah INTCON 10Bh EEDATL 10Ch EEADRL 10Dh EEDATH 10Eh EEADRH 10Fh LCDDATA0 110h LCDDATA1 111h LCDDATA2 112h LCDDATA3 113h LCDDATA4 114h LCDDATA5 115h LCDDATA6 116h LCDDATA7 117h LCDDATA8 118h LCDDATA9 119h LCDDATA10 11Ah LCDDATA11 11Bh LCDSE0 11Ch LCDSE1 11Dh LCDSE2 11Eh 11Fh 120h General Purpose Register 80 Bytes accesses 70h-7Fh Bank 2 16Fh 170h 17Fh accesses 70h-7Fh Bank 3 1EFh 1F0h 1FFh File Address Indirect addr. (1) 180h OPTION_REG 181h PCL 182h STATUS 183h FSR 184h 185h TRISB 186h 187h 188h 189h PCLATH 18Ah INTCON 18Bh EECON1 18Ch EECON2(1) 18Dh 18Eh 18Fh 190h File Address Indirect addr. (1) 00h TMR0 01h PCL 02h STATUS 03h FSR 04h PORTA 05h PORTB 06h PORTC 07h PORTD 08h PORTE 09h PCLATH 0Ah INTCON 0Bh PIR1 0Ch PIR2 0Dh TMR1L 0Eh TMR1H 0Fh T1CON 10h TMR2 11h T2CON 12h SSPBUF 13h SSPCON 14h CCPR2L 15h CCPR2H 16h CCP2CON 17h RCSTA 18h TXREG 19h RCREG 1Ah CCPR2L 1Bh CCPR2H 1Ch CCPR2CON 1Dh ADRESH 1Eh ADCON0 1Fh 20h
General Purpose Register(2) 96 Bytes
General Purpose Register
Note 1: 2:
Unimplemented data memory locations, read as `0'. Not a physical register. On the PIC16F914, unimplemented data memory locations, read as `0'.
DS41250E-page 16
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
TABLE 2-1:
Addr Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh(2) 1Ch(2) 1Dh(2) 1Eh 1Fh INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(2) PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx RA4 RB4 RC4 RD4 -- RA3 RB3 RC3 RD3 RE3 RA2 RB2 RC2 RD2 RE2(2) RA1 RB1 RC1 RD1 RE1(2) RA0 RB0 RC0 RD0 RE0(2) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ---- xxxx ---0 0000 RBIF TMR1IF CCP2IF 0000 000x 0000 0000 0000 -0-0 xxxx xxxx xxxx xxxx TMR1CS TMR1ON 0000 0000 0000 0000 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 xxxx xxxx SSPM2 SSPM1 SSPM0 0000 0000 xxxx xxxx xxxx xxxx CCP1M3 ADDEN CCP1M2 FERR CCP1M1 OERR CCP1M0 RX9D --00 0000 0000 000x 0000 0000 0000 0000 xxxx xxxx xxxx xxxx CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 xxxx xxxx CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 xxxx xxxx uuuu uuuu 0000 0000 000q quuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu ---0 0000 0000 000x 0000 0000 0000 -0-0 uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 -000 0000 uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu --00 0000 0000 000x 0000 0000 0000 0000 uuuu uuuu uuuu uuuu --00 0000 uuuu uuuu 0000 0000 Name
PIC16F917/916/914/913 SPECIAL REGISTERS SUMMARY BANK 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Reset Value on all other Resets(1)
Indirect Data Memory Address Pointer RA7 RB7 RC7 RD7 -- -- GIE EEIF OSFIF RA6 RB6 RC6 RD6 -- -- PEIE ADIF C2IF RA5 RB5 RC5 RD5 -- -- T0IE RCIF C1IF
Write Buffer for upper 5 bits of Program Counter INTE TXIF LCDIF RBIE SSPIF -- T0IF CCP1IF LVDIF INTF TMR2IF --
Holding Register for the Least Significant Byte of the 16-bit TMR1 Holding Register for the Most Significant Byte of the 16-bit TMR1 T1GINV T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Timer2 Module Register -- TOUTPS3
Synchronous Serial Port Receive Buffer/Transmit Register WCOL SSPOV SSPEN CKP SSPM3
Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) -- SPEN -- RX9 CCP1X SREN CCP1Y CREN
USART Transmit Data Register USART Receive Data Register Capture/Compare/PWM Register 2 (LSB) Capture/Compare/PWM Register 2 (MSB) -- -- CCP2X CCP2Y
A/D Result Register High Byte ADFM VCFG1 VCFG0
Legend: Note 1: 2:
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. PIC16F914/917 only.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 17
PIC16F917/916/914/913
TABLE 2-2:
Addr Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh INDF OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD(2) TRISE PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE ANSEL PR2 SSPADD SSPSTAT WPUB IOCB CMCON1 TXSTA SPBRG -- -- CMCON0 VRCON ADRESL ADCON1 Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU IRP TRISA7 TRISB7 TRISC7 TRISD7 -- -- GIE EEIE OSFIE -- -- -- ANS7(3) INTEDG RP1 TRISA6 TRISB6 TRISC6 TRISD6 -- -- PEIE ADIE C2IE -- IRCF2 -- ANS6(3) T0CS RP0 TRISA5 TRISB5 TRISC5 TRISD5 -- -- T0IE RCIE C1IE -- IRCF1 -- ANS5(3) T0SE TO TRISA4 TRISB4 TRISC4 TRISD4 -- INTE TXIE LCDIE SBOREN IRCF0 TUN4 ANS4 PSA PD TRISA3 TRISB3 TRISC3 TRISD3 PS2 Z TRISA2 TRISB2 TRISC2 TRISD2 PS1 DC TRISA1 TRISB1 TRISC1 TRISD1 PS0 C TRISA0 TRISB0 TRISC0 TRISD0 Program Counter's (PC) Least Significant Byte Indirect Data Memory Address Pointer xxxx xxxx 1111 1111 0000 0000 0001 1xxx xxxx xxxx 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---0 0000 0000 000x 0000 0000 0000 -0-0 ---1 --qq -110 q000 ---0 0000 1111 1111 1111 1111 0000 0000 R/W WPUB2 -- -- BRGH SPBRG2 UA WPUB1 -- T1GSS TRMT SPBRG1 BF WPUB0 -- C2SYNC TX9D SPBRG0 0000 0000 1111 1111 0000 ------- --10 0000 -010 0000 0000 -- -- C2INV VRR ADCS1 C1INV -- ADCS0 CIS VR3 -- CM2 VR2 -- CM1 VR1 -- CM0 VR0 -- 0000 0000 0-0- 0000 xxxx xxxx -000 ---D/A WPUB5 IOCB5 -- TXEN SPBRG5 P WPUB4 IOCB4 -- SYNC SPBRG4 S WPUB3 -- -- -- SPBRG3 xxxx xxxx 1111 1111 0000 0000 000q quuu uuuu uuuu 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---0 0000 0000 000x 0000 0000 0000 -0-0 ---u --uu -110 x000 ---u uuuu 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 0000 ------- --10 0000 -010 0000 0000 -- -- 0000 0000 0-0- 0000 uuuu uuuu -000 --Name
PIC16F917/916/914/913 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Reset Value on all other Resets(1)
TRISE3(5) TRISE2(2) TRISE1(2) TRISE0(2) RBIE SSPIE -- -- OSTS(4) TUN3 ANS3 T0IF CCP1IE LVDIE -- HTS TUN2 ANS2 INTF TMR2IE -- POR LTS TUN1 ANS1 RBIF TMR1IE CCP2IE BOR SCS TUN0 ANS0
Write Buffer for the upper 5 bits of the Program Counter
Timer2 Period Register Synchronous Serial Port (I2C mode) Address Register SMP WPUB7 IOCB7 -- CSRC SPBRG7 CKE WPUB6 IOCB6 -- TX9 SPBRG6
Unimplemented Unimplemented C2OUT VREN -- C1OUT -- ADCS2
A/D Result Register Low Byte
Legend: Note 1: 2: 3: 4: 5:
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. PIC16F914/917 only. PIC16F914/917 only, forced `0' on PIC16F913/916. The value of the OSTS bit is dependent on the value of the Configuration Word (CONFIG) of the device. See Section 4.0 "Clock Sources". Bit is read-only; TRISE = 1 always.
DS41250E-page 18
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
TABLE 2-3:
Addr Bank 2 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h INDF TMR0 PCL STATUS FSR WDTCON PORTB LCDCON LCDPS LVDCON Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu WDTPS2 RB3 CS1 LP3 -- WDTPS1 RB2 CS0 LP2 LVDL2 WDTPS0 RB1 LMUX1 LP1 LVDL1 SWDTEN RB0 LMUX0 LP0 LVDL0 ---0 1000 ---0 1000 xxxx xxxx uuuu uuuu 0001 0011 0001 0011 0000 0000 0000 0000 --00 -100 --00 -100 ---0 0000 ---0 0000 0000 000x 0000 000x 0000 0000 0000 0000 Name
PIC16F917/916/914/913 SPECIAL REGISTERS SUMMARY BANK 2
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Reset Value on all other Resets(1)
Indirect Data Memory Address Pointer -- RB7 LCDEN WFT -- -- GIE EEDATL7 -- RB6 SLPEN BIASMD -- -- PEIE EEDATL6 -- RB5 WERR LCDA IRVST -- T0IE EEDATL5 WDTPS3 RB4 VLCDEN WA LVDEN
10Ah PCLATH 10Bh INTCON 10Ch EEDATL 10Dh EEADRL 10Eh EEDATH 10Fh EEADRH 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh LCDDATA0 LCDDATA1 LCDDATA2(2) LCDDATA3 LCDDATA4 LCDDATA5(2) LCDDATA6 LCDDATA7 LCDDATA8(2) LCDDATA9 LCDDATA10 LCDDATA11(2)
Write Buffer for the upper 5 bits of the Program Counter INTE EEDATL4 RBIE EEDATL3 EEADRL3 EEDATH3 T0IF EEDATL2 EEADRL2 EEDATH2 INTF EEDATL1 EEADRL1 EEDATH1 RBIF EEDATL0
EEADRL7 EEADRL6 EEADRL5 EEADRL4 -- -- SEG7 COM0 SEG15 COM0 SEG23 COM0 SEG7 COM1 SEG15 COM1 SEG23 COM1 SEG7 COM2 SEG15 COM2 SEG23 COM2 SEG7 COM3 SEG15 COM3 SEG23 COM3 SE7 SE15 SE23 -- -- SEG6 COM0 SEG14 COM0 SEG22 COM0 SEG6 COM1 SEG14 COM1 SEG22 COM1 SEG6 COM2 SEG14 COM2 SEG22 COM2 SEG6 COM3 SEG14 COM3 SEG22 COM3 SE6 SE14 SE22 EEDATH5 EEDATH4 -- SEG5 COM0 SEG13 COM0 SEG21 COM0 SEG5 COM1 SEG13 COM1 SEG21 COM1 SEG5 COM2 SEG13 COM2 SEG21 COM2 SEG5 COM3 SEG13 COM3 SEG21 COM3 SE5 SE13 SE21
EEADRL0 0000 0000 0000 0000 EEDATH0 --00 0000 --00 0000
EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---0 0000 ---0 0000 SEG4 COM0 SEG12 COM0 SEG20 COM0 SEG4 COM1 SEG12 COM1 SEG20 COM1 SEG4 COM2 SEG12 COM2 SEG20 COM2 SEG4 COM3 SEG12 COM3 SEG20 COM3 SE4 SE12 SE20 SEG3 COM0 SEG11 COM0 SEG19 COM0 SEG3 COM1 SEG11 COM1 SEG19 COM1 SEG3 COM2 SEG11 COM2 SEG19 COM2 SEG3 COM3 SEG11 COM3 SEG19 COM3 SE3 SE11 SE19 SEG2 COM0 SEG10 COM0 SEG18 COM0 SEG2 COM1 SEG10 COM1 SEG18 COM1 SEG2 COM2 SEG10 COM2 SEG18 COM2 SEG2 COM3 SEG10 COM3 SEG18 COM3 SE2 SE10 SE18 SEG1 COM0 SEG9 COM0 SEG17 COM0 SEG1 COM1 SEG9 COM1 SEG17 COM1 SEG1 COM2 SEG9 COM2 SEG17 COM2 SEG1 COM3 SEG9 COM3 SEG17 COM3 SE1 SE9 SE17 SEG0 COM0 SEG8 COM0 SEG16 COM0 SEG0 COM1 SEG8 COM1 SEG16 COM1 SEG0 COM2 SEG8 COM2 SEG16 COM2 SEG0 COM3 SEG8 COM3 SEG16 COM3 SE0 SE8 SE16 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 uuuu uuuu 0000 0000 uuuu uuuu 0000 0000 uuuu uuuu -- --
11Ch LCDSE0(3) 11Dh LCDSE1(3) 11Eh 11Fh Legend: Note 1: 2: 3: LCDSE2(2,3) --
Unimplemented
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. PIC16F914/917 only. This register is only initialized by a POR or BOR reset and is unchanged by other Resets.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 19
PIC16F917/916/914/913
TABLE 2-4:
Addr Bank 3 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh Legend: Note 1: INDF Addressing this location uses contents of FSR to address data memory (not a physical register) PSA PD PS2 Z PS1 DC PS0 C xxxx xxxx 1111 1111 0000 0000 0001 1xxx xxxx xxxx -- TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 -- -- -- -- Write Buffer for the upper 5 bits of the Program Counter T0IF WREN INTF WR RBIF RD ---0 0000 0000 000x 0--- x000 ---- ---xxxx xxxx 1111 1111 0000 0000 000q quuu uuuu uuuu -- 1111 1111 -- -- -- ---0 0000 0000 000x 0--- q000 ---- ---Name
PIC16F917/916/914/913 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Reset Value on all other Resets(1)
INTEDG T0CS T0SE OPTION_REG RBPU PCL Program Counter (PC) Least Significant Byte STATUS FSR -- TRISB -- -- -- PCLATH INTCON EECON1 EECON2 IRP RP1 RP0 TO Indirect Data Memory Address Pointer Unimplemented TRISB7 TRISB6 Unimplemented Unimplemented Unimplemented -- GIE EEPGD -- PEIE
T0IE INTE RBIE WRERR -- -- -- EEPROM Control Register 2 (not a physical register)
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
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Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
2.2.2.1 Status Register
The Status register, shown in Register 2-1, contains: * the arithmetic status of the ALU * the Reset status * the bank select bits for data memory (SRAM) The Status register can be the destination for any instruction, like any other register. If the Status register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the Status register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the Status register as `000u u1uu' (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the Status register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (see Section 17.0 "Instruction Set Summary"). Note 1: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 2-1:
STATUS - STATUS REGISTER (ADDRESS: 03h, 83h, 103h OR 183h)
R/W-0 IRP bit 7 R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh) RP<1:0>: Register Bank Select bits (used for direct addressing) 00 = Bank 0 (00h-7Fh) 01 = Bank 1 (80h-FFh) 10 = Bank 2 (100h-17Fh) 11 = Bank 3 (180h-1FFh) TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 21
PIC16F917/916/914/913
2.2.2.2 Option Register
Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT by setting PSA bit to `1' (OPTION_REG<3>). See Section 5.4 "Prescaler". The Option register is a readable and writable register, which contains various control bits to configure: * * * * TMR0/WDT prescaler External RB0/INT interrupt TMR0 Weak pull-ups on PORTB
REGISTER 2-2:
OPTION_REG - OPTION REGISTER (ADDRESS: 81h OR 181h)
R/W-1 RBPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
bit 7
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT/SEG0 pin 0 = Interrupt on falling edge of RB0/INT/SEG0 pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/C1OUT/T0CKI/SEG4 pin 0 = Internal instruction cycle clock (CLKO) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/C1OUT/T0CKI/SEG4 pin 0 = Increment on low-to-high transition on RA4/C1OUT/T0CKI/SEG4 pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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2.2.2.3 INTCON Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTB change and external RB0/INT/SEG0 pin interrupts.
REGISTER 2-3:
INTCON - INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh OR 18Bh)
R/W-0 GIE bit 7 R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit 0
bit 7
GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT/SEG0 External Interrupt Enable bit 1 = Enables the RB0/INT/SEG0 external interrupt 0 = Disables the RB0/INT/SEF0 external interrupt RBIE: PORTB Change Interrupt Enable bit(1) 1 = Enables the PORTB change interrupt 0 = Disables the PORTB change interrupt T0IF: TMR0 Overflow Interrupt Flag bit(2) 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT/SEG0 External Interrupt Flag bit 1 = The RB0/INT/SEG0 external interrupt occurred (must be cleared in software) 0 = The RB0/INT/SEG0 external interrupt did not occur RBIF: PORTB Change Interrupt Flag bit 1 = When at least one of the PORTB <5:0> pins changed state (must be cleared in software) 0 = None of the PORTB <7:4> pins have changed state Note 1: IOCB register must also be enabled. 2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing T0IF bit. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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Preliminary
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PIC16F917/916/914/913
2.2.2.4 PIE1 Register
Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. The PIE1 register contains the interrupt enable bits, as shown in Register 2-1.
REGISTER 2-4:
PIE1 - PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
R/W-0 EEIE bit 7 R/W-0 ADIE R/W-0 RCIE R/W-0 TXIE R/W-0 SSPIE R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE bit 0
bit 7
EEIE: EE Write Complete Interrupt Enable bit 1 = Enabled 0 = Disabled ADIE: A/D Converter Interrupt Enable bit 1 = Enabled 0 = Disabled RCIE: USART Receive Interrupt Enable bit 1 = Enabled 0 = Disabled TXIE: USART Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit 1 = Enabled 0 = Disabled CCP1IE: CCP1 Interrupt Enable bit 1 = Enabled 0 = Disabled TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enabled 0 = Disabled TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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2.2.2.5 PIE2 Register
Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. The PIE2 register contains the interrupt enable bits, as shown in Register 2-5.
REGISTER 2-5:
PIE2 - PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS: 8Dh)
R/W-0 OSFIE bit 7 R/W-0 C2IE R/W-0 C1IE R/W-0 LCDIE U-0 -- R/W-0 LVDIE U-0 -- R/W-0 CCP2IE bit 0
bit 7
OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled C2IE: Comparator 2 Interrupt Enable bit 1 = Enables Comparator 2 interrupt 0 = Disables Comparator 2 interrupt C1IE: Comparator 1 Interrupt Enable bit 1 = Enables Comparator 1 interrupt 0 = Disables Comparator 1 interrupt LCDIE: LCD Module Interrupt Enable bit 1 = LCD interrupt is enabled 0 = LCD interrupt is disabled Unimplemented: Read as `0' LVDIE: Low Voltage Detect Interrupt Enable bit 1 = Enables LVD Interrupt 0 = Disables LVD Interrupt Unimplemented: Read as `0' CCP2IE: CCP2 Interrupt Enable bit (only available in 16F914/917) 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1 bit 0
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Preliminary
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PIC16F917/916/914/913
2.2.2.6 PIR1 Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR1 register contains the interrupt flag bits, as shown in Register 2-6.
REGISTER 2-6:
PIR1 - PERIPHERAL INTERRUPT REQUEST REGISTER 1 (ADDRESS: 0Ch)
R/W-0 EEIF bit 7 R/W-0 ADIF R-0 RCIF R-0 TXIF R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0
bit 7
EEIF: EE Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not started ADIF: A/D Converter Interrupt Flag bit 1 = The A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (cleared by reading RCREG) 0 = The USART receive buffer is not full TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty (cleared by writing to TXREG) 0 = The USART transmit buffer is full SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit 1 = The Transmission/Reception is complete (must be cleared in software) 0 = Waiting to Transmit/Receive CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode Unused in this mode TMR2IF: TMR2 to PR2 Interrupt Flag bit 1 = A TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = The TMR1 register overflowed (must be cleared in software) 0 = The TMR1 register did not overflow Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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PIC16F917/916/914/913
2.2.2.7 PIR2 Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR2 register contains the interrupt flag bits, as shown in Register 2-7.
REGISTER 2-7:
PIR2 - PERIPHERAL INTERRUPT REQUEST REGISTER 2 (ADDRESS: 0Dh)
R/W-0 OSFIF bit 7 R/W-0 C2IF R-0 C1IF R-0 LCDIF U-0 -- R/W-0 LVDIF U-0 -- R/W-0 CCP2IF bit 0
bit 7
OSFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = System clock operating C2IF: Comparator 2 Interrupt Flag bit 1 = Comparator output (C2OUT bit) has changed (must be cleared in software) 0 = Comparator output (C2OUT bit) has not changed C1IF: Comparator 1 Interrupt Flag bit 1 = Comparator output (C1OUT bit) has changed (must be cleared in software) 0 = Comparator output (C1OUT bit) has not changed LCDIF: LCD Module Interrupt bit 1 = LCD has generated an interrupt 0 = LCD has not generated an interrupt Unimplemented: Read as `0' LVDIF: Low Voltage Detect Interrupt Flag bit 1 = LVD has generated an interrupt 0 = LVD has not generated an interrupt Unimplemented: Read as `0' CCP2IF: CCP2 Interrupt Flag bit (only available in 16F914/917) Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode Unused in this mode Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1 bit 0
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Preliminary
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PIC16F917/916/914/913
2.2.2.8 PCON Register
The Power Control (PCON) register (See Table 17-2) contains flag bits to differentiate between a: * * * * Power-on Reset (POR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset
The PCON register also controls the software enable of the BOR. The PCON register bits are shown in Register 2-8.
REGISTER 2-8:
PCON - POWER CONTROL REGISTER (ADDRESS: 8Eh)
U-0 -- bit 7 U-0 -- U-0 -- R/W-1 SBOREN U-0 -- U-0 -- R/W-0 POR R/W-x BOR bit 0
bit 7-5 bit 4
Unimplemented: Read as `0' SBOREN: Software BOR Enable bit(1) 1 = BOR enabled 0 = BOR disabled Unimplemented: Read as `0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: BOREN<1:0> = 01 in the Configuration Word register for this bit to control the BOR. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 3-2 bit 1
bit 0
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PIC16F917/916/914/913
2.3 PCL and PCLATH
Note 1: There are no Status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in Figure 2-5 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in Figure 2-5 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH).
2.4
Program Memory Paging
FIGURE 2-5:
PCH 12 PC 5 8 7
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 0 Instruction with PCL as Destination ALU Result
PCLATH<4:0>
8
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 OPCODE<10:0> PCLATH 11 10 8 7 PCL 0 GOTO, CALL
All PIC16F917/916/914/913 devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is POPed off the stack. Therefore, manipulation of the PCLATH<4:3> bits is not required for the RETURN instructions (which POPs the address from the stack). Note: The contents of the PCLATH register are unchanged after a RETURN or RETFIE instruction is executed. The user must rewrite the contents of the PCLATH register for any subsequent subroutine calls or GOTO instructions.
2.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, "Implementing a Table Read" (DS00556).
Example 2-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the Interrupt Service Routine (if interrupts are used).
EXAMPLE 2-1:
CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0
2.3.2
STACK
ORG 0x500 BCF PCLATH,4 BSF PCLATH,3 CALL SUB1_P1 : : ORG 0x900 SUB1_P1 : : RETURN
The PIC16F917/916/914/913 family has an 8-level x 13-bit wide hardware stack (see Figures 2-1 and 2-2). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth PUSH overwrites the value that was stored from the first PUSH. The tenth PUSH overwrites the second PUSH (and so on).
;Select page 1 ;(800h-FFFh) ;Call subroutine in ;page 1 (800h-FFFh) ;page 1 (800h-FFFh) ;called subroutine ;page 1 (800h-FFFh) ;return to ;Call subroutine ;in page 0 ;(000h-7FFh)
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Preliminary
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PIC16F917/916/914/913
2.5 Indirect Addressing, INDF and FSR Registers
EXAMPLE 2-2:
MOVLW MOVWF NEXTCLRF INCF BTFSS GOTO CONTINUE 0x20 FSR INDF FSR FSR,4 NEXT
INDIRECT ADDRESSING
;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-6. A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 2-2.
FIGURE 2-6:
DIRECT/INDIRECT ADDRESSING PIC16F917/916/914/913
Indirect Addressing 0 IRP 7 File Select Register 0
Direct Addressing RP1 RP0 6 From Opcode
Bank Select
Location Select 00 00h 01 10 11
Bank Select 180h
Location Select
Data Memory
7Fh Bank 0 Note: Bank 1 Bank 2 Bank 3
1FFh
For memory map detail, see Figures 2-3 and 2-4.
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PIC16F917/916/914/913
3.0 I/O PORTS
EXAMPLE 3-1:
BCF BCF CLRF BSF BCF MOVLW MOVWF CLF MOVLW MOVWF BCF BCF STATUS,RP0 STATUS,RP1 PORTA STATUS,RP0 STATUS,RP1 07h CMCON0 ANSEL F0h TRISA STATUS,RP0 STATUS,RP1
INITIALIZING PORTA
;Bank 0 ; ;Init PORTA ;Bank 1 ; ;Set RA<2:0> to ;digital I/O ;Make all PORTA I/O ;Set RA<7:4> as inputs ;and set RA<3:0> ; as outputs ;Bank 0 ;
This device includes four 8-bit port registers along with their corresponding TRIS registers and one four bit port: * * * * * PORTA and TRISA PORTB and TRISB PORTC and TRISC PORTD and TRISD PORTE and TRISE
PORTA, PORTB, PORTC and RE3/MCLR/VPP are implemented on all devices. PORTD and RE<2:0> are implemented only on the PIC16F914 and PIC16F917.
3.1
PORTA and TRISA Registers
PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 3-2). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Example 3-1 shows how to initialize PORTA. Five of the pins of PORTA can be configured as analog inputs. These pins, RA5 and RA<3:0>, are configured as analog inputs on device power-up and must be reconfigured by the user to be used as I/O's. This is done by writing the appropriate values to the CMCON0 and ANSEL registers (see Example 3-1). Reading the PORTA register (Register 3-1) reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch. The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. Note 1: The CMCON0 (9Ch) register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'. 2: Analog lines that carry LCD signals (i.e., SEGx, COMy, where x and y are segment and common identifiers) are shown as direct connections to the device pins. The signals are outputs from the LCD module and may be tri-stated, depending on the configuration of the LCD module.
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Preliminary
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PIC16F917/916/914/913
REGISTER 3-1: PORTA - PORTA REGISTER (ADDRESS: 05h)
R/W-x RA7 bit 7 bit 7-0 RA<7:0>: PORTA I/O Pin bits 1 = Port pin is >VIH 0 = Port pin is REGISTER 3-2:
TRISA - PORTA TRI-STATE REGISTER (ADDRESS: 85h)
R/W-1 TRISA7 bit 7 R/W-1 TRISA6 R/W-1 TRISA5 R/W-1 TRISA4 R/W-1 TRISA3 R/W-1 TRISA2 R/W-1 TRISA1 R/W-1 TRISA0 bit 0
bit 7-0
TRISA<7:0>: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output Note: Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TRISA<7:6> always reads `1' in XT, HS and LP OSC modes.
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PIC16F917/916/914/913
3.1.1 PIN DESCRIPTIONS AND DIAGRAMS
Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions, refer to the appropriate section in this data sheet.
3.1.1.1
RA0/AN0/C1-/SEG12
Figure 3-1 shows the diagram for this pin. The RA0/AN0/C1-/SEG12 pin is configurable to function as one of the following: * * * * a general purpose I/O an analog input for the A/D an analog input for Comparator 1 an analog output for the LCD
FIGURE 3-1:
BLOCK DIAGRAM OF RA0/AN0/C1-/SEG12
Data Bus D CK Q Q VDD
WR PORTA
Data Latch D WR TRISA CK Q I/O Pin Q Analog Input or SE12 and LCDEN RD TRISA SE12 and LCDEN TTL Input Buffer
TRIS Latch
RD PORTA SEG12 SE12 and LCDEN To A/D Converter or Comparator
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Preliminary
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PIC16F917/916/914/913
3.1.1.2 RA1/AN1/C2-/SEG7
Figure 3-2 shows the diagram for this pin. The RA1/AN1/C2-/SEG7 pin is configurable to function as one of the following: * * * * a general purpose I/O an analog input for the A/D an analog input for Comparator 2 an analog output for the LCD
FIGURE 3-2:
BLOCK DIAGRAM OF RA1/AN1/C2-/SEG7
Data Bus D CK Q Q VDD
WR PORTA
Data Latch D WR TRISA CK Q I/O Pin Q Analog Input or SE7 and LCDEN RD TRISA SE7 and LCDEN TTL Input Buffer
TRIS Latch
RD PORTA SEG7 SE7 and LCDEN To A/D Converter or Comparator
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3.1.1.3 RA2/AN2/C2+/VREF-/COM2
Figure 3-3 shows the diagram for this pin. The RA2/AN2/C2+/VREF-/COM2 pin is configurable to function as one of the following: * * * * * a general purpose I/O an analog input for the A/D an analog input for Comparator 2 a voltage reference input for the A/D an analog output for the LCD
FIGURE 3-3:
BLOCK DIAGRAM OF RA2/AN2/C2+/VREF-/COM2
Data Bus
D CK
Q Q VDD
WR PORTA
Data Latch D WR TRISA CK Q I/O Pin Q Analog Input or LCDEN and LMUX<1:0> = 1X LCDEN and LMUX<1:0> = 1X TTL Input Buffer
TRIS Latch
RD TRISA
RD PORTA LCDEN and LMUX<1:0> = 1X
COM2
To A/D Converter or Comparator To A/D Module VREF- Input
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Preliminary
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PIC16F917/916/914/913
3.1.1.4 RA3/AN3/C1+/VREF+/COM3/SEG15
Figure 3-4 shows the diagram for this pin. The pin is RA3/AN3/C1+/VREF+/COM3/SEG15 configurable to function as one of the following: * * * * * a general purpose input an analog input for the A/D an analog input from Comparator 1 a voltage reference input for the A/D analog outputs for the LCD
FIGURE 3-4:
BLOCK DIAGRAM OF RA3/AN3/C1+/VREF+/COM3/SEG15
Data Bus WR PORTA
D CK
Q VDD Q
Data Latch D WR TRISA CK Q Q VSS Analog Input or LCDMODE_EN(2) TTL Input Buffer I/O Pin
TRIS Latch
RD TRISA
LCDMODE_EN(2)
RD PORTA COM3(1) or SEG15 LCDMODE_EN(2)
To A/D Converter or Comparator To A/D Module VREF+ Input
Note 1: 2:
PIC16F913/916 only. For the PIC16F913/916, the LCDMODE_EN = LCDEN and (SE15 or LMUX<1:0> = 11). For the PIC16F914/917, the LCDMODE_EN = LCDEN and SE15.
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3.1.1.5 RA4/C1OUT/T0CKI/SEG4
Figure 3-5 shows the diagram for this pin. The RA4/C1OUT/T0CKI/SEG4 pin is configurable to function as one of the following: * * * * a general purpose I/O a digital output from Comparator 1 a clock input for TMR0 an analog output for the LCD
FIGURE 3-5:
BLOCK DIAGRAM OF RA4/C1OUT/T0CKI/SEG4
CM<2:0> = 110 or 101 C1OUT Data Bus WR PORTA D CK Q Q I/O Pin VSS Analog Input or SE4 and LCDEN RD TRISA SE4 and LCDEN TTL Input Buffer 1 0 VDD
Data Latch D WR TRISA CK Q Q
TRIS Latch
RD PORTA SE4 and LCDEN T0CKI SE4 and LCDEN SEG4 Schmitt Trigger
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PIC16F917/916/914/913
3.1.1.6 RA5/AN4/C2OUT/SS/SEG5
Figure 3-6 shows the diagram for this pin. The RA5/AN4/C2OUT/SS/SEG5 pin is configurable to function as one of the following: * * * * * a general purpose I/O a digital output from Comparator 2 a slave select input an analog output for the LCD an analog input for the A/D
FIGURE 3-6:
BLOCK DIAGRAM OF RA5/AN4/C2OUT/SS/SEG5
CM<2:0> = 110 or 101 C2OUT Data Bus D CK Q Q I/O Pin VSS Analog Input or SE5 and LCDEN SE5 and LCDEN TTL Input Buffer 1 0 VDD
WR PORTA
Data Latch D WR TRISA CK Q Q
TRIS Latch
RD TRISA
RD PORTA To SS Input SE5 and LCDEN SEG5 AN4
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PIC16F917/916/914/913
3.1.1.7 RA6/OSC2/CLKO/T1OSO
Figure 3-7 shows the diagram for this pin. The RA6/OSC2/CLKO/T1OSO pin is configurable to function as one of the following: * * * * a general purpose I/O a crystal/resonator connection a clock output a TMR1 oscillator connection
FIGURE 3-7:
BLOCK DIAGRAM OF RA6/OSC2/CLKO/T1OSO
From OSC1 Oscillator Circuit 1 0 VDD
FOSC = 1x1 CLKO (FOSC/4) Data Bus WR PORTA D CK Q Q
Data Latch D WR TRISA FOSC = 00x, 010 or T1OSCEN CK Q Q FOSC = 00x, 010 or T1OSCEN TTL Input Buffer RD TRISA VSS RA6/OSC2/ CLKO/T1OSO Pin
TRIS Latch
RD PORTA
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 39
PIC16F917/916/914/913
3.1.1.8 RA7/OSC1/CLKI/T1OSI
Figure 3-8 shows the diagram for this pin. The RA7/OSC1/CLKI/T1OSI pin is configurable to function as one of the following: * * * * a general purpose I/O a crystal/resonator connection a clock input a TMR1 oscillator connection
FIGURE 3-8:
BLOCK DIAGRAM OF RA7/OSC1/CLKI/T1OSI
From OSC1 Oscillator Circuit
FOSC = 011
Data Bus WR PORTA
D CK
Q Q VDD
Data Latch
D WR TRISA FOSC = 10x CK
Q Q FOSC = 10x TTL Input Buffer RD TRISA
RA7/OSC1/ CLKI/T1OSI Pin
TRIS Latch
RD PORTA
TABLE 3-1:
Address 05h 10h 14h 1Fh Name PORTA T1CON SSPCON ADCON0
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 RA7 T1GINV WCOL ADFM RBPU TRISA7 ANS7 C2OUT LCDEN SE7 SE15 Bit 6 RA6 T1GE SSPOV VCFG1 INTEDG TRISA6 ANS6 C1OUT SLPEN SE6 SE14 Bit 5 RA5 Bit 4 RA4 Bit 3 RA3 Bit 2 RA2 Bit 1 RA1 TMR1CS SSPM1 GO/DONE PS1 TRISA1 ANS1 CM1 LMUX1 SE1 SE9 Bit 0 RA0 Value on: POR, BOR Value on all other Resets
xxxx xxxx uuuu uuuu
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC SSPEN VCFG0 T0CS TRISA5 ANS5 C2INV WERR SE5 SE13 CKP CHS2 T0SE TRISA4 ANS4 C1INV VLCDEN SE4 SE12 SSPM3 CHS1 PSA TRISA3 ANS3 CIS CS1 SE3 SE11 SSPM2 CHS0 PS2 TRISA2 ANS2 CM2 CS0 SE2 SE10
TMR1ON 0000 0000 uuuu uuuu SSPM0 ADON PS0 TRISA0 ANS0 CM0 LMUX0 SE0 SE8 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0001 0011 0001 0011 0000 0000 uuuu uuuu 0000 0000 uuuu uuuu
81h/181h OPTION_REG 85h 91h 9Ch 107h 11Ch 11Dh Legend: Note 1: TRISA ANSEL CMCON0 LCDCON LCDSE0(1) LCDSE1(1)
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTA. This register is only initialized by a POR or BOR reset and is unchanged by other Resets.
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PIC16F917/916/914/913
3.2 PORTB and TRISB Registers 3.3 Additional PORTB Pin Functions
PORTB is a general purpose I/O port with similar functionality as the PIC16F77. All PORTB pins can have a weak pull-up feature, and PORTB<7:4> implements an interrupt-on-input change function. PORTB is also used for the Serial Flash programming interface. Note: Analog lines that carry LCD signals (i.e., SEGx, COMy, where x and y are segment and common identifiers) are shown as direct connections to the device pins. The signals are outputs from the LCD module and may be tri-stated, depending on the configuration of the LCD module. RB<7:6> are used as data and clock signals, respectively, for both serial programming and the in-circuit debugger features on the device. Also, RB0 can be configured as an external interrupt input.
3.3.1
WEAK PULL-UPS
Each of the PORTB pins has an individually configurable internal weak pull-up. Control bits WPUB<7:0> enable or disable each pull-up. Refer to Register 3-6. Each weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset by the RBPU bit (OPTION_REG<7>).
3.3.2
INTERRUPT-ON-CHANGE
EXAMPLE 3-2:
BCF BCF CLRF BSF BCF MOVLW MOVWF BCF BCF STATUS,RP0 STATUS,RP1 PORTB STATUS,RP0 STATUS,RP1 FFh TRISB STATUS,RP0 STATUS,RP1
INITIALIZING PORTB
;Bank 0 ; ;Init PORTB ;Bank 1 ; ;Set RB<7:0> as inputs ; ;Bank 0 ;
Four of the PORTB pins are individually configurable as an interrupt-on-change pin. Control bits IOCB<7:4> enable or disable the interrupt function for each pin. Refer to Register 3-5. The interrupt-on-change feature is disabled on a Power-on Reset. For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of PORTB. The `mismatch' outputs of the last read are OR'd together to set the PORTB Change Interrupt flag bit (RBIF) in the INTCON register (Register 2-3). This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the interrupt by: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear the flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF. Reading or writing PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The latch holding the last read value is not affected by a MCLR nor Brown-out Reset. After these Resets, the RBIF flag will continue to be set if a mismatch is present. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set. Furthermore, since a read or write on a port affects all bits of that port, care must be taken when using multiple pins in Interrupt-on-change mode. Changes on one pin may not be seen while servicing changes on another pin.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 41
PIC16F917/916/914/913
REGISTER 3-3: PORTB - PORTB REGISTER (ADDRESS: 06h OR 106h)
R/W-x RB7 bit 7 bit 7-0 RB<7:0>: PORTB I/O Pin bits 1 = Port pin is >VIH 0 = Port pin is REGISTER 3-4:
TRISB - PORTB TRI-STATE REGISTER (ADDRESS: 86h, 186h)
R/W-1 TRISB7 bit 7 R/W-1 TRISB6 R/W-1 TRISB5 R/W-1 TRISB4 R/W-1 TRISB3 R/W-1 TRISB2 R/W-1 TRISB1 R/W-1 TRISB0 bit 0
bit 7-0
TRISB<7:0>: PORTB Tri-State Control bits 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output Note: Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TRISB<7:6> always reads `1' in XT, HS and LP OSC modes.
REGISTER 3-5:
IOCB - PORTB INTERRUPT-ON-CHANGE REGISTER (ADDRESS: 96h)
R/W-0 IOCB7 bit 7 R/W-0 IOCB6 R/W-0 IOCB5 R/W-0 IOCB4 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 7-4
IOCB<7:4>: Interrupt-on-Change bits 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Unimplemented: Read as `0' Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 3-0
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REGISTER 3-6: WPUB - WEAK PULL-UP REGISTER (ADDRESS: 95h)
R/W-1 WPUB7 bit 7 bit 7-0 WPUB<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global RBPU must be enabled for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISB<7:0> = 0). Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 WPUB6 R/W-1 WPUB5 R/W-1 WPUB4 R/W-1 WPUB3 R/W-1 WPUB2 R/W-1 WPUB1 R/W-1 WPUB0 bit 0
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3.3.3 PIN DESCRIPTIONS AND DIAGRAMS
Each PORTB pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the LCD or interrupts, refer to the appropriate section in this data sheet.
3.3.3.1
RB0/INT/SEG0
Figure 3-9 shows the diagram for this pin. The RB0/INT/SEG0 pin is configurable to function as one of the following: * a general purpose I/O * an external edge triggered interrupt * an analog output for the LCD
3.3.3.2
RB1/SEG1
Figure 3-9 shows the diagram for this pin. The RB1/SEG1 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.3.3.3
RB2/SEG2
Figure 3-9 shows the diagram for this pin. The RB2/SEG2 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.3.3.4
RB3/SEG3
Figure 3-9 shows the diagram for this pin. The RB3/SEG3 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
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FIGURE 3-9:
RBPU(1) Data Bus WR PORTB D CK Data Latch D WR TRISB CK TRIS Latch SE<3:0> and LCDEN TTL Input Buffer RD TRISB Q Q I/O Pin
BLOCK DIAGRAM OF RB<3:0>
SE<3:0> VDD VDD P Weak Pull-up
RD PORTB SEG<3:0> INT(2) SE<3:0> and LCDEN SE0 and LCDEN Schmitt Trigger
Note 1: 2:
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. RB0 only.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 45
PIC16F917/916/914/913
3.3.3.5 RB4/COM0
Figure 3-10 shows the diagram for this pin. The RB4/COM0 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
FIGURE 3-10:
BLOCK DIAGRAM OF RB4/COM0
LCDEN RBPU
(1)
VDD VDD P Weak Pull-up
Data Bus WR PORTB
D CK
Q I/O Pin
Data Latch D WR TRISB CK TRIS Latch LCDEN TTL Input Buffer RD TRISB Q
RD PORTB Set RBIF LCDEN From other RB<7:4> pins
Q
D EN RD PORTB
Q
D EN FOSC/4
COM0
LCDEN
Note 1:
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
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3.3.3.6 RB5/COM1
Figure 3-11 shows the diagram for this pin. The RB5/COM1 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
FIGURE 3-11:
BLOCK DIAGRAM OF RB5/COM1
LCDEN and LMUX<1:0> 00 VDD VDD P Weak Pull-up D CK Data Latch D Q Q I/O Pin
RBPU(1) Data Bus WR PORTB
WR TRISB
CK TRIS Latch LCDEN and LMUX<1:0> 00 TTL Input Buffer RD TRISB Q RD PORTB D EN LCDEN and LMUX<1:0> 00 Q D EN LCDEN and LMUX<1:0> 00 RD PORTB FOSC/4
Set RBIF From other RB<7:4> pins
COM1 Note 1:
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 47
PIC16F917/916/914/913
3.3.3.7 RB6/ICSPCLK/ICDCK/SEG14
Figure 3-12 shows the diagram for this pin. The RB6/ICSPCLK/ICDCK/SEG14 pin is configurable to function as one of the following: * * * * a general purpose I/O an In-Circuit Serial ProgrammingTM clock an ICD clock I/O an analog output for the LCD
FIGURE 3-12:
BLOCK DIAGRAM OF RB6/ICSPCLK/ICDCK/SEG14
Program Mode/ICD RBPU(1) SE14 and LCDEN Data Bus WR PORTB D CK Data Latch D WR TRISB CK TRIS Latch SE14 and LCDEN RD TRISB Q RD PORTB Set RBIF Program Mode/ICD From other RB<7:4> pins SE14 and LCDEN PGC Schmitt Trigger Buffer Q D EN D EN Q Q
VDD P Weak Pull-up VDD
I/O Pin
TTL Input Buffer
RD PORTB
FOSC/4
SE14 and LCDEN SEG14
Note 1:
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
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PIC16F917/916/914/913
3.3.3.8 RB7/ICSPDAT/ICDDAT/SEG13
Figure 3-13 shows the diagram for this pin. The RB7/ICSPDAT/ICDDAT/SEG13 pin is configurable to function as one of the following: * * * * a general purpose I/O an In-Circuit Serial ProgrammingTM I/O an ICD data I/O an analog output for the LCD
FIGURE 3-13:
BLOCK DIAGRAM OF RB7/ICSPDAT/ICDDAT/SEG13
PORT/Program Mode/ICD PGD RBPU(1) SE13 and LCDEN
VDD Weak P Pull-up 1 0 I/O Pin
VDD
Data Bus WR PORTB
D CK
Q
Data Latch D WR TRISB CK TRIS Latch 0 PGD DRVEN 1 TTL Input Buffer RD TRISB SE13 and LCDEN Q RD PORTB Set RBIF From other RB<7:4> pins SE13 and LCDEN PGD SEG13 Schmitt Trigger Buffer Q D EN FOSC/4 D EN Program Mode/ICD RD PORTB Q
SE13 and LCDEN
Note 1:
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 49
PIC16F917/916/914/913
TABLE 3-2:
Address 06h/106h 86h/186h 0Bh/8Bh/ 10Bh/18Bh 95h 96h 107h 11Ch 11Dh Legend: Note 1: Name PORTB TRISB INTCON WPUB IOCB LCDCON LCDSE0(1) LCDSE1(1)
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7 RB7 TRISB7 GIE WPUB7 IOCB7 LCDEN SE7 SE15 Bit 6 RB6 TRISB6 PEIE WPUB6 IOCB6 SLPEN SE6 SE14 Bit 5 RB5 TRISB5 T0IE WPUB5 IOCB5 WERR SE5 SE13 Bit 4 RB4 TRISB4 INTE WPUB4 IOCB4 VLCDEN SE4 SE12 Bit 3 RB3 TRISB3 RBIE WPUB3 -- CS1 SE3 SE11 Bit 2 RB2 TRISB2 T0IF WPUB2 -- CS0 SE2 SE10 Bit 1 RB1 TRISB1 INTF WPUB1 -- LMUX1 SE1 SE9 Bit 0 RB0 TRISB0 RBIF WPUB0 -- LMUX0 SE0 SE8 Value on: POR, BOR xxxx xxxx 1111 1111 0000 000x 1111 1111 0000 ---0001 0011 0000 0000 0000 0000 Value on all other Resets uuuu uuuu 1111 1111 0000 000x 1111 1111 0000 ---0001 0011 uuuu uuuu uuuu uuuu
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTB. This register is only initialized by a POR or BOR reset and is unchanged by other Resets.
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3.4 PORTC and TRISC Registers
EXAMPLE 3-3:
BCF BCF CLRF BSF BCF MOVLW MOVWF BCF BSF CLRF BCF BCF STATUS,RP0 STATUS,RP1 PORTC STATUS,RP0 STATUS,RP1 FFh TRISC STATUS,RP0 STATUS,RP1 LCDCON
INITIALIZING PORTC
PORTC is an 8-bit bidirectional port. PORTC is multiplexed with several peripheral functions. PORTC pins have Schmitt Trigger input buffers. All PORTC pins have latch bits (PORTC register). They, when written, will modify the contents of the PORTC latch; thus, modifying the value driven out on a pin if the corresponding TRISC bit is configured for output. Note: Analog lines that carry LCD signals (i.e., SEGx, VLCDy, where x and y are segment and LCD bias voltage identifiers) are shown as direct connections to the device pins. The signals are outputs from the LCD module and may be tri-stated, depending on the configuration of the LCD module.
;Bank 0 ; ;Init PORTC ;Bank 1 ; ;Set RC<7:0> as inputs ; ;Bank 2 ; ;Disable VLCD<3:1> ;inputs on RC<2:0> STATUS,RP0 ;Bank 0 STATUS,RP1 ;
REGISTER 3-7:
PORTC - PORTC REGISTER (ADDRESS: 07h)
R/W-x RC7 bit 7 R/W-x RC6 R/W-x RC5 R/W-x RC4 R/W-x RC3 R/W-x RC2 R/W-x RC1 R/W-x RC0 bit 0
bit 7-0
RC<7:0>: PORTC I/O Pin bits 1 = Port pin is >VIH 0 = Port pin is REGISTER 3-8:
TRISC - PORTC TRI-STATE REGISTER (ADDRESS: 87h)
R/W-1 TRISC7 bit 7 R/W-1 TRISC6 R/W-1 TRISC5 R/W-1 TRISC4 R/W-1 TRISC3 R/W-1 TRISC2 R/W-1 TRISC1 R/W-1 TRISC0 bit 0
bit 7-0
TRISC<7:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output Note: Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TRISC<7:6> always reads `1' in XT, HS and LP OSC modes.
(c) 2005 Microchip Technology Inc.
Preliminary
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3.4.1 PIN DESCRIPTIONS AND DIAGRAMS 3.4.1.3 RC2/VLCD3
Each PORTC pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the LCD or SSP, refer to the appropriate section in this data sheet. Figure 3-16 shows the diagram for this pin. The RC2/VLCD3 pin is configurable to function as one of the following: * a general purpose I/O * an analog input for the LCD bias voltage
3.4.1.1
RC0/VLCD1
Figure 3-14 shows the diagram for this pin. The RC0/VLCD1 pin is configurable to function as one of the following: * a general purpose I/O * an analog input for the LCD bias voltage
3.4.1.2
RC1/VLCD2
Figure 3-15 shows the diagram for this pin. The RC1/VLCD2 pin is configurable to function as one of the following: * a general purpose I/O * an analog input for the LCD bias voltage
FIGURE 3-14:
Data Bus WR PORTC
BLOCK DIAGRAM OF RC0/VLCD1
VDD
D
Q
Q CK Data Latch D Q Q
RC0/VLCD1 Pin
WR TRISC
CK
TRIS Latch (VLCDEN and LMUX<1:0> 00) RD TRISC Schmitt Trigger
RD PORTC (VLCDEN and LMUX<1:0> 00)
VLCD1
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FIGURE 3-15: BLOCK DIAGRAM OF RC1/VLCD2
Data Bus WR PORTC
D CK D
Q Q Q Q
VDD
Data Latch
RC1/VLCD2 Pin
WR TRISC
CK
TRIS Latch (VLCDEN and LMUX<1:0> 00) RD TRISC Schmitt Trigger
RD PORTC (VLCDEN and LMUX<1:0> 00)
VLCD2
FIGURE 3-16:
BLOCK DIAGRAM OF RC2/VLCD3
Data Bus WR PORTC
D CK D
Q Q Q Q
VDD
Data Latch
RC2/VLCD3 Pin
WR TRISC
CK
TRIS Latch
VLCDEN RD TRISC Schmitt Trigger
RD PORTC VLCDEN
VLCD3
(c) 2005 Microchip Technology Inc.
Preliminary
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3.4.1.4 RC3/SEG6
Figure 3-17 shows the diagram for this pin. The RC3/SEG6 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
FIGURE 3-17:
BLOCK DIAGRAM OF RC3/SEG6
Data Bus WR PORTC
D CK D
Q Q Q
VDD
Data Latch
RC3/SEG6 Pin
WR TRISC
Q CK TRIS Latch
SE6 and LCDEN RD TRISC Schmitt Trigger
RD PORTC SE6 and LCDEN
SEG6 and LCDEN
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3.4.1.5 RC4/T1G/SDO/SEG11
Figure 3-18 shows the diagram for this pin. The RC4//T1G/SDO/SEG11pin is configurable to function as one of the following: * * * * a general purpose I/O a TMR1 gate input a serial data output an analog output for the LCD
FIGURE 3-18:
BLOCK DIAGRAM OF RC4/T1G/SDO/SEG11
PORT/SDO Select SDO 0 1 VDD
Data Bus WR PORTC
D
Q
CK Q Data Latch D Q Q VSS RC4/T1G/ SDO/SEG11 Pin
WR TRISC
CK
TRIS Latch
RD TRISC
SE11 and LCDEN
Schmitt Trigger
RD PORTC Timer1 Gate SE11 and LCDEN SEG11
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 55
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3.4.1.6 RC5/T1CKI/CCP1/SEG10
Figure 3-19 shows the diagram for this pin. The RC5/T1CKI/CCP1/SEG10 pin is configurable to function as one of the following: * * * * a general purpose I/O a TMR1 clock input a Capture input, Compare output or PWM output an analog output for the LCD
FIGURE 3-19:
BLOCK DIAGRAM OF RC5/T1CKI/CCP1/SEG10
(PORT/CCP1 Select) and CCPMX CCP1 Data Out 0 Data Bus WR PORTC D CK Q Q RC5/T1CKI/ CCP1/SEG10 Pin VSS 1 VDD
Data Latch D WR TRISC CK Q Q
TRIS Latch
RD TRISC
SE10 and LCDEN
Schmitt Trigger
RD PORTC Timer1 Gate SEG10 SE10 and LCDEN
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3.4.1.7 RC6/TX/CK/SCK/SCL/SEG9
Figure 3-20 shows the diagram for this pin. The RC6/TX/CK/SCK/SCL/SEG9 pin is configurable to function as one of the following: * * * * * * a general purpose I/O an asynchronous serial output a synchronous clock I/O a SPI clock I/O an I2C data I/O an analog output for the LCD
FIGURE 3-20:
BLOCK DIAGRAM OF RC6/TX/CK/SCK/SCL/SEG9
PORT/SCEN/SSP Mode Select(1) I2CTM Data Out TX/CK Data Out SCK Data Out Data Bus WR PORTC D CK Q Q RC6/TX/ CK/SCK/ SCL/SEG9 VSS Pin 0 1 2 3 VDD
Data Latch D WR TRISC CK Q Q
TRIS Latch
SCEN or I2CTM Drive
RD TRISC
SE9 and LCDEN
Schmitt Trigger
RD PORTC CK/SCL/SCK Input SE9 and LCDEN SEG9
Note 1:
If all three data output sources are enabled, the following priority order will be used: * USART data * SSP data * PORT data
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3.4.1.8 RC7/RX/DT/SDI/SDA/SEG8
Figure 3-21 shows the diagram for this pin. The RC7/RX/DT/SDI/SDA/SEG8 pin is configurable to function as one of the following: * * * * * * a general purpose I/O an asynchronous serial input a synchronous serial data I/O a SPI data I/O an I2C data I/O an analog output for the LCD
FIGURE 3-21:
BLOCK DIAGRAM OF RC7/RX/DT/SDI/SDA/SEG8
SCEN/I2CTM Mode Select(1) DT Data Out I2CTM Data Out
0 1
PORT/(SCEN or I2CTM) Select 0 1 Data Bus WR PORTC
VDD
D CK
Q Q
RC7/RX/DT/ SDI/SDA/ SEG8 Pin
Data Latch D Q
WR TRISC
CK
Q
SE8 and LCDEN
TRIS Latch Schmitt Trigger
I2CTM Drive or SCEN Drive
RD TRISC
RD PORTC RX/SDI Input SE8 and LCDEN SEG8
Note 1:
If SSP and USART outputs are both enabled, the USART data output will have priority over the SSP data output. Both SSP and USART data outputs will have priority over the PORT data output.
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TABLE 3-3:
Address 07h 10h 14h 17h 18h 87h 107h 11Ch 11Dh Legend: Note 1: Name PORTC T1CON SSPCON CCP1CON RCSTA TRISC LCDCON LCDSE0(1) LCDSE1(1)
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7 RC7 T1GINV WCOL -- SPEN TRISC7 LCDEN SE7 SE15 Bit 6 RC6 T1GE SSPOV -- RX9 TRISC6 SLPEN SE6 SE14 Bit 5 RC5 Bit 4 RC4 Bit 3 RC3 Bit 2 RC2 Bit 1 RC1 TMR1CS SSPM1 CCP1M1 OERR TRISC1 LMUX1 SE1 SE9 Bit 0 RC0 Value on: POR, BOR Value on all other Resets
xxxx xxxx uuuu uuuu
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC SSPEN CCP1X SREN TRISC5 WERR SE5 SE13 CKP CCP1Y CREN TRISC4 VLCDEN SE4 SE12 SSPM3 CCP1M3 ADDEN TRISC3 CS1 SE3 SE11 SSPM2 CCP1M2 FERR TRISC2 CS0 SE2 SE10
TMR1ON 0000 0000 uuuu uuuu SSPM0 CCP1M0 RX9D TRISC0 LMUX0 SE0 SE8 0000 0000 0000 0000 --00 0000 0000 000x --00 0000 0000 000x
1111 1111 1111 1111 0001 0011 0001 0011 0000 0000 uuuu uuuu 0000 0000 uuuu uuuu
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTC. This register is only initialized by a POR or BOR reset and is unchanged by other Resets.
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Preliminary
DS41250E-page 59
PIC16F917/916/914/913
3.5 PORTD and TRISD Registers
EXAMPLE 3-4:
BCF BCF CLRF BSF BCF MOVLW MOVWF BCF BCF STATUS,RP0 STATUS,RP1 PORTD STATUS,RP0 STATUS,RP1 FFh TRISD STATUS,RP0 STATUS,RP1
INITIALIZING PORTD
;Bank 0 ; ;Init PORTD ;Bank 1 ; ;Set RD<7:0> as inputs ; ;Bank 0 ;
PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configured as an input or output. PORTD is only available on the PIC16F914 and PIC16F917. Note: Analog lines that carry LCD signals (i.e., SEGx, COMy, where x and y are segment and common identifiers) are shown as direct connections to the device pins. The signals are outputs from the LCD module and may be tri-stated, depending on the configuration of the LCD module.
REGISTER 3-9:
PORTD - PORTD REGISTER (ADDRESS: 08h)
R/W-x RD7 bit 7 R/W-x RD6 R/W-x RD5 R/W-x RD4 R/W-x RD3 R/W-x RD2 R/W-x RD1 R/W-x RD0 bit 0
bit 7-0
RD<7:0>: PORTD I/O Pin bits 1 = Port pin is >VIH 0 = Port pin is REGISTER 3-10:
TRISD - PORTD TRI-STATE REGISTER (ADDRESS: 88h)
R/W-1 TRISD7 bit 7 R/W-1 TRISD6 R/W-1 TRISD5 R/W-1 TRISD4 R/W-1 TRISD3 R/W-1 TRISD2 R/W-1 TRISD1 R/W-1 TRISD0 bit 0
bit 7-0
TRISD<7:0>: PORTD Tri-State Control bits 1 = PORTD pin configured as an input (tri-stated) 0 = PORTD pin configured as an output Note: Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TRISD<7:6> always reads `1' in XT, HS and LP OSC modes.
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Preliminary
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PIC16F917/916/914/913
3.5.1 PIN DESCRIPTIONS AND DIAGRAMS 3.5.1.7 RD6/SEG19
Each PORTD pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the A/D, refer to the appropriate section in this data sheet. Figure 3-25 shows the diagram for this pin. The RD6/SEG19 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.5.1.1
RD0/COM3
3.5.1.8
RD7/SEG20
Figure 3-22 shows the diagram for this pin. The RD0/COM3 pin is configurable to function as one of the following: * a general purpose I/O * an analog input for the A/D
Figure 3-25 shows the diagram for this pin. The RD7/SEG20 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.5.1.2
RD1
Figure 3-23 shows the diagram for this pin. The RD1 pin is configurable to function as one of the following: * a general purpose I/O
3.5.1.3
RD2/CCP2
Figure 3-24 shows the diagram for this pin. The RD2/CCP2 pin is configurable to function as one of the following: * a general purpose I/O * a Capture input, Compare output or PWM output
3.5.1.4
RD3/SEG16
Figure 3-25 shows the diagram for this pin. The RD3/SEG16 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.5.1.5
RD4/SEG17
Figure 3-25 shows the diagram for this pin. The RD4/SEG17 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.5.1.6
RD5/SEG18
Figure 3-25 shows the diagram for this pin. The RD5/SEG18 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 61
PIC16F917/916/914/913
FIGURE 3-22: BLOCK DIAGRAM OF RD0/COM3
VDD Data Bus WR PORTD
D CK
Q Q RD0/COM3 Pin
Data Latch D WR TRISD CK Q Q Schmitt Trigger RD TRISD LCDEN and LMUX<1:0> = 11
TRIS Latch
RD PORTD LCDEN and LMUX<1:0> = 11
COM3
FIGURE 3-23:
BLOCK DIAGRAM OF RD1
VDD
Data Bus WR PORTD
D CK
Q Q RD1 Pin
Data Latch D WR TRISD CK Q Q
TRIS Latch Schmitt Trigger RD TRISD
RD PORTD
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Preliminary
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PIC16F917/916/914/913
FIGURE 3-24: BLOCK DIAGRAM OF RD2/CCP2
(PORT/CCP2 Select) and CCPMX VDD CCP2 Data Out 0 Data Bus WR PORTD
D CK
Q Q
1
RD2/CCP2 Pin
Data Latch D
WR TRISD
Q Q Schmitt Trigger
CK
TRIS Latch
RD TRISD
RD PORTD CCP2 Input
FIGURE 3-25:
BLOCK DIAGRAM OF RD<7:3>
VDD
Data Bus WR PORTD
D CK
Q Q RD<7:3> Pin
Data Latch D WR TRISD CK Q Q
TRIS Latch SE<20:16> and LCDEN RD TRISD
Schmitt Trigger
RD PORTD SE<20:16> and LCDEN SEG<20:16>
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Preliminary
DS41250E-page 63
PIC16F917/916/914/913
TABLE 3-4:
Address Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR xxxx xxxx --00 0000 1111 1111 0001 0011 0000 0000 Value on all other Resets uuuu uuuu --00 0000 1111 1111 0001 0011 uuuu uuuu
08h 1Dh(2) 88h 107h 11Eh Legend: Note 1: 2:
PORTD CCP2CON TRISD(2) LCDCON LCDSE2
(1,2)
RD7 -- TRISD7 LCDEN SE23
RD6 -- TRISD6 SLPEN SE22
RD5 CCP2X TRISD5 WERR SE21
RD4 CCP2Y TRISD4 VLCDEN SE20
RD3 CCP2M3 TRISD3 CS1 SE19
RD2 CCP2M2 TRISD2 CS0 SE18
RD1 CCP2M1 TRISD1 LMUX1 SE17
RD0 CCP2M0 TRISD0 LMUX0 SE16
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTC. This register is only initialized by a POR or BOR reset and is unchanged by other Resets. PIC16F914/917 only.
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Preliminary
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PIC16F917/916/914/913
3.6 PORTE and TRISE Registers
EXAMPLE 3-5:
BCF BCF CLRF BSF BCF MOVLW MOVWF CLRF BCF BCF STATUS,RP0 STATUS,RP1 PORTE STATUS,RP0 STATUS,RP1 0Fh TRISE ANSEL STATUS,RP0 STATUS,RP1
INITIALIZING PORTE
;Bank 0 ; ;Init PORTE ;Bank 1 ; ;Set RE<3:0> as inputs ; ;Make RE<2:0> as I/O's ;Bank 0 ;
PORTE is a 4-bit port with Schmitt Trigger input buffers. RE<2:0> are individually configured as inputs or outputs. RE3 is only available as an input if MCLRE is `0' in Configuration Word (Register 16-1). RE<2:0> are only available on the PIC16F914 and PIC16F917. Note: Analog lines that carry LCD signals (i.e., SEGx, where x are segment identifiers) are shown as direct connections to the device pins. The signals are outputs from the LCD module and may be tri-stated, depending on the configuration of the LCD module.
REGISTER 3-11:
PORTE - PORTE REGISTER (ADDRESS: 09h)
U-0 -- bit 7 U-0 -- U-0 -- U-0 -- R/W-x RE3 R/W-x RE2 R/W-x RE1 R/W-x RE0 bit 0
bit 7-4 bit 3-0
Unimplemented: Read as `0' RE<3:0>: PORTE I/O Pin bits 1 = Port pin is >VIH 0 = Port pin is REGISTER 3-12:
TRISE - PORTE TRI-STATE REGISTER (ADDRESS: 89h)
U-0 -- bit 7 U-0 -- U-0 -- U-0 -- R-1 TRISE3 R/W-1 TRISE2 R/W-1 TRISE1 R/W-1 TRISE0 bit 0
bit 7-4 bit 3 bit 2-0
Unimplemented: Read as `0' TRISE3: Data Direction bit. RE3 is always an input, so this bit always reads as a `1' TRISE<2:0>: Data Direction bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 65
PIC16F917/916/914/913
3.6.1 PIN DESCRIPTIONS AND DIAGRAMS 3.6.1.3 RE2/AN7/SEG23
Each PORTE pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the A/D, refer to the appropriate section in this data sheet. Figure 3-26 shows the diagram for this pin. The RE2/AN7/SEG23 pin is configurable to function as one of the following: * a general purpose I/O * an analog input for the A/D * an analog output for the LCD
3.6.1.1
RE0/AN5/SEG21
Figure 3-26 shows the diagram for this pin. The RE0/AN5/SEG21pin is configurable to function as one of the following: * a general purpose I/O * an analog input for the A/D * an analog output for the LCD
3.6.1.4
RE3/MCLR/VPP
Figure 3-27 shows the diagram for this pin. The RE3/MCLR/VPP pin is configurable to function as one of the following: * a digital input only * as Master Clear Reset with weak pull-up * a programming voltage reference input
3.6.1.2
RE1/AN6/SEG22
Figure 3-26 shows the diagram for this pin. The RE1/AN6/SEG22 pin is configurable to function as one of the following: * a general purpose I/O * an analog input for the A/D * an analog output for the LCD
FIGURE 3-26:
BLOCK DIAGRAM OF RE<2:0>
VDD
Data Bus WR PORTE
D CK
Q Q RE<2:0> Pin
Data Latch D WR TRISE CK Q Q Analog Mode or SE<23:21> and LCDEN RD TRISE Schmitt Trigger
TRIS Latch
RD PORTE SE<23:21> and LCDEN SEG<23:21> AN<7:5>
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Preliminary
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PIC16F917/916/914/913
FIGURE 3-27: BLOCK DIAGRAM OF RE3/MCLR/VPP
MCLR circuit
MCLR Filter(1)
HV Schmitt Trigger Buffer
Programming mode
HV Detect MCLRE RE3/MCLR/VPP
Data Bus
HV Schmitt Trigger Buffer RE TRIS
RE Port
Note 1:
The MCLR filter is bypassed in Emulation mode.
TABLE 3-5:
Address 09h 1Fh 89h 91h 107h 11Eh Legend: Note 1: 2: 3: Name PORTE ADCON0 TRISE ANSEL LCDCON
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 7 -- ADFM -- ANS7 LCDEN SE23 Bit 6 -- VCFG1 -- ANS6 SLPEN SE22 Bit 5 -- VCFG0 -- ANS5 WERR SE21 Bit 4 -- CHS2 -- ANS4 VLCDEN SE20 Bit 3 RE3 CHS1 TRISE3(3) ANS3 CS1 SE19 Bit 2 RE2 CHS0 TRISE2(2) ANS2 CS0 SE18 Bit 1 RE1 GO/DONE TRISE1(2) ANS1 LMUX1 SE17 Bit 0 RE0 ADON Value on: POR, BOR Value on all other Resets
---- xxxx ---- uuuu 0000 0000 0000 0000
TRISE0(2) ---- 1111 ---- 1111 ANS0 LMUX0 SE16 1111 1111 1111 1111 0001 0011 0001 0011 0000 0000 uuuu uuuu
LCDSE2(1,2)
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTC. This register is only initialized by a POR or BOR reset and is unchanged by other Resets. PIC16F914/917 only. Bit is read-only; TRISE = 1 always.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 67
PIC16F917/916/914/913
NOTES:
DS41250E-page 68
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
4.0
4.1
CLOCK SOURCES
Overview
The PIC16F917/916/914/913 can be configured in one of eight clock modes. 1. 2. 3. 4. 5. 6. 7. 8. EC - External clock with I/O on RA6. LP - Low-gain Crystal or Ceramic Resonator Oscillator mode. XT - Medium-gain Crystal or Ceramic Resonator Oscillator mode. HS - High-gain Crystal or Ceramic Resonator mode. RC - External Resistor-Capacitor (RC) with FOSC/4 output on RA6. RCIO - External Resistor-Capacitor with I/O on RA6. INTOSC - Internal oscillator with FOSC/4 output on RA6 and I/O on RA7. INTOSCIO - Internal oscillator with I/O on RA6 and RA7.
The PIC16F917/916/914/913 has a wide variety of clock sources and selection features to allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 4-1 illustrates a block diagram of the PIC16F917/916/914/913 clock sources. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators, and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured from one of two internal oscillators, with a choice of speeds selectable via software. Additional clock features include: * Selectable system clock source between external or internal via software. * Two-Speed Clock Start-up mode, which minimizes latency between external oscillator start-up and code execution. * Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch to the Internal Oscillator.
Clock source modes are configured by the FOSC<2:0> bits in the Configuration Word register (see Section 16.0 "Special Features of the CPU"). The internal clock can be generated by two oscillators. The HFINTOSC is a high-frequency calibrated oscillator. The LFINTOSC is a low-frequency uncalibrated oscillator.
FIGURE 4-1:
PIC16F917/916/914/913 SYSTEM CLOCK BLOCK DIAGRAM
FOSC<2:0> (Configuration Word) SCS (OSCCON<0>)
External Oscillator OSC2 Sleep OSC1
LP, XT, HS, RC, RCIO, EC MUX IRCF<2:0> (OSCCON<6:4>) 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 31 kHz 111 110 101 100 011 010 001 000
System Clock (CPU and Peripherals)
Internal Oscillator Postscaler HFINTOSC 8 MHz LFINTOSC 31 kHz
MUX
LCD Module Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM)
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Preliminary
DS41250E-page 69
PIC16F917/916/914/913
REGISTER 4-1: OSCCON - OSCILLATOR CONTROL REGISTER (ADDRESS: 8Fh)
U-0 -- bit 7 bit 7 bit 6-4 R/W-1 IRCF2 R/W-1 IRCF1 R/W-0 IRCF0 R-q OSTS(1) R-0 HTS R-0 LTS R/W-0 SCS bit 0
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as `0' IRCF<2:0>: Internal Oscillator Frequency Select bits 000 = 31 kHz 001 = 125 kHz 010 = 250 kHz 011 = 500 kHz 100 = 1 MHz 101 = 2 MHz 110 = 4 MHz 111 = 8 MHz OSTS: Oscillator Start-up Time-out Status bit 1 = Device is running from the external system clock defined by FOSC<2:0> 0 = Device is running from the internal system clock (HFINTOSC or LFINTOSC) HTS: HFINTOSC (High Frequency - 8 MHz to 125 kHz) Status bit 1 = HFINTOSC is stable 0 = HFINTOSC is not stable LTS: LFINTOSC (Low Frequency - 31 kHz) Stable bit 1 = LFINTOSC is stable 0 = LFINTOSC is not stable SCS: System Clock Select bit 1 = Internal oscillator is used for system clock 0 = Clock source defined by FOSC<2:0> Note 1: The value of the OSTS bit on device power-up is dependent on the value of the Configuration Word (CONFIG) of the device. The value of the OSTS bit will be `0' on a device Power-on Reset (POR) or any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, if the following conditions are true: OSTS = 0 if: FOSC<2:0> = 000 (LP) or 001 (XT) or 010 (HS) and IESO = 1 or FSCM = 1 (IESO will be enabled automatically if FSCM is enabled) If any of the above conditions are not met, the value of the OSTS bit will be `1' on a device POR. See Section 4.6 "Two-Speed Clock Start-up Mode" and Section 4.7 "Fail-Safe Clock Monitor" for more details. Legend: R = Readable bit W = Writable bit - n = Value at POR `1' = Bit is set q = value depends on condition
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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PIC16F917/916/914/913
4.2 Clock Source Modes
4.3.1.1 Special Case
Clock source modes can be classified as external or internal. * External clock modes rely on external circuitry for the clock source. Examples are oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes), and Resistor-Capacitor (RC mode) circuits. * Internal clock sources are contained internally within the PIC16F917/916/914/913. The PIC16F917/916/914/913 has two internal oscillators: the 8 MHz High-Frequency Internal Oscillator (HFINTOSC) and 31 kHz Low-Frequency Internal Oscillator (LFINTOSC). The system clock can be selected between external or internal clock sources via the System Clock Selection (SCS) bit (see Section 4.5 "Clock Switching"). An exception to this is when the device is put to Sleep while the following conditions are true: * LP is the selected primary oscillator mode. * T1OSCEN = 1 (Timer1 oscillator is enabled). * SCS = 0 (oscillator mode is defined by FOSC<2:0>). * OSTS = 1 (device is running from primary system clock). For this case, the OST is not necessary after a wake-up from Sleep, since Timer1 continues to run during Sleep and uses the same LP oscillator circuit as its clock source. For these devices, this case is typically seen when the LCD module is running during Sleep. In applications where the OSCTUNE register is used to shift the FINTOSC frequency, the application should not expect the FINTOSC frequency to stabilize immediately. In this case, the frequency may shift gradually toward the new value. The time for this frequency shift is less than eight cycles of the base frequency. Note: When the OST is invoked, the WDOG is held in Reset, because the WDOG ripple counter is used by the OST to perform the oscillator delay count. When the OST count has expired, the WDOG will begin counting (if enabled).
4.3
4.3.1
External Clock Modes
OSCILLATOR START-UP TIMER (OST)
If the PIC16F917/916/914/913 is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from the OSC1 pin, following a Power-on Reset (POR), and the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the PIC16F917/916/914/913. When switching between clock sources a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 4-1.
Table 4-1 shows examples where the oscillator delay is invoked. In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 4.6 "Two-Speed Clock Start-up Mode").
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 71
PIC16F917/916/914/913
TABLE 4-1:
System Clock Source LFIOSC
OSCILLATOR DELAY EXAMPLES
Frequency 31 kHz Switching From Sleep Oscillator Delay (TOST) Comments
10 s internal delay Following a wake-up from Sleep mode or POR, an internal delay is invoked to allow the memory bias to stabilize before program execution can begin. 10 s internal delay Following a wake-up from Sleep mode or POR, an internal delay is invoked to allow the memory bias to stabilize before program execution can begin. 1024 clock cycles 1024 clock cycles Following a change from INTOSC, an OST of 1024 cycles must occur. Following a change from INTOSC, an OST of 1024 cycles must occur. See Section 4.3.1.1 "Special Case" for special case conditions.
HFIOSC
125 kHz-8 MHz
Sleep
XT or HS LP
4-20 MHz 32 kHz
INTOSC or Sleep INTOSC or Sleep
LP with T1OSC enabled
32 kHz
Sleep
10 s internal delay Following a wake-up from Sleep mode, an internal delay is invoked to allow the memory bias to stabilize before program execution can begin. See Section 4.3.1.1 "Special Case" for details about this special case. 10 s internal delay Following a wake-up from Sleep mode or POR, an internal delay is invoked to allow the memory bias to stabilize before program execution can begin. 10 s internal delay Following a switch from a LFIOSC or POR, an internal delay is invoked to allow the memory bias to stabilize before program execution can begin.
EC, RC
0-20 MHz
Sleep
EC, RC
0-20 MHz
LFIOSC
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PIC16F917/916/914/913
4.3.2 EC MODE 4.3.3 LP, XT, HS MODES
The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 pin and the RA6 pin is available for general purpose I/O. Figure 4-2 shows the pin connections for EC mode. The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC16F917/916/914/913 design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to the OSC1 and OSC2 pins (Figures 4-3 and 4-4). The mode selects a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is best suited to drive resonators with a low drive level specification, for example, tuning fork type crystals. Note: In the past, the sources for the LP oscillator and Timer1 oscillator have been separate circuits. In this family of devices, the LP oscillator and Timer1 oscillator use the same oscillator circuitry. When using a device configured for the LP oscillator and with T1OSCEN = 1, the source of the clock for each function comes from the same oscillator block.
FIGURE 4-2:
EXTERNAL CLOCK (EC) MODE OPERATION
PIC16F917/916/914/913
Clock (External System)
OSC1/ CLKIN
FOSC
Internal Clock
FOSC<2:0> = 011 RA6 RA6/OSC2/CLKO/T1OSO
XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification, for example, low-frequency/AT-cut quartz crystal resonators. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting, for example, high-frequency/AT-cut quartz crystal resonators or ceramic resonators. Figures 4-3 and 4-4 show typical circuits for quartz crystal and ceramic resonators, respectively.
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Preliminary
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PIC16F917/916/914/913
FIGURE 4-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE)
PIC16F917/916/914/913 OSC1 C1 Quartz Crystal OSC2 RS(1) C2 Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. 2: The value of RF varies with the oscillator mode selected (typically between 2 M to 10 M). 3: If using LP mode and T1OSC in enable, the LP oscillator will continue to run during Sleep. Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. RF
(2)
FIGURE 4-4:
CERAMIC RESONATOR OPERATION (XT OR HS MODE)
PIC16F917/916/914/913 OSC1
To Int. Logic Sleep(3)
C1 RF
(3)
RF
(2)
To Int. Logic Sleep
OSC2 RS(1) Ceramic C2 Resonator Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the oscillator mode selected (typically between 2 M to 10 M). 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation (typical value 1 M).
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PIC16F917/916/914/913
4.3.4 EXTERNAL RC MODES
4.4
Internal Clock Modes
The External Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes, RC and RCIO. In RC mode, the RC circuit connects to the OSC1 pin. The OSC2/CLKO pin outputs the RC oscillator frequency divided by 4. This signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. Figure 4-5 shows the RC mode connections.
The PIC16F917/916/914/913 has two independent, internal oscillators that can be configured or selected as the system clock source. 1. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 8 MHz. The frequency of the HFINTOSC can be user adjusted 12% via software using the OSCTUNE register (Register 4-2). The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at approximately 31 kHz.
2.
FIGURE 4-5:
VDD
RC MODE
PIC16F917/916/914/913
The system clock speed can be selected via software using the Internal Oscillator Frequency Select (IRCF) bits. The system clock can be selected between external or internal clock sources via the System Clock Selection (SCS) bit (see Section 4.5 "Clock Switching").
REXT OSC1 CEXT VSS FOSC/4 OSC2/CLKO Internal Clock
4.4.1
INTOSC AND INTOSCIO MODES
Recommended values: 3 k REXT 100 k CEXT > 20 pF In RCIO mode, the RC circuit is connected to the OSC1 pin. The OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 4 of PORTA (RA4). Figure 4-6 shows the RCIO mode connections.
The INTOSC and INTOSCIO modes configure the internal oscillators as the system clock source when the device is programmed using the Oscillator Selection (FOSC) bits in the Configuration Word register (Register 16-1). In INTOSC mode, the OSC1 pin is available for general purpose I/O. The OSC2/CLKO pin outputs the selected internal oscillator frequency divided by 4. The CLKO signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. In INTOSCIO mode, the OSC1 and OSC2 pins are available for general purpose I/O.
FIGURE 4-6:
VDD
RCIO MODE
PIC16F917/916/914/913
4.4.2
HFINTOSC
REXT OSC1 CEXT VSS RA6 Recommended values:3 k REXT 100 k CEXT > 20 pF The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal threshold voltage. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency or for low CEXT values. The user also needs to take into account variation due to tolerance of external RC components used. I/O (OSC2) Internal Clock
The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 8 MHz internal clock source. The frequency of the HFINTOSC can be altered approximately 12% via software using the OSCTUNE register (Register 4-2). The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 4-1). One of seven frequencies can be selected via software using the IRCF bits (see Section 4.4.4 "Frequency Select Bits (IRCF)"). The HFINTOSC is enabled by selecting any frequency between 8 MHz and 125 kHz (IRCF 000) as the System Clock Source (SCS = 1), or when Two-Speed Start-up is enabled (IESO = 1 and IRCF 000). The HF Internal Oscillator (HTS) bit (OSCCON<2>) indicates whether the HFINTOSC is stable or not.
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4.4.2.1 OSCTUNE Register
The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 4-2). The OSCTUNE register has a tuning range of 12%. The default value of the OSCTUNE register is `0'. The value is a 5-bit two's complement number. Due to process variation, the monotonicity and frequency step cannot be specified. When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. The HFINTOSC clock will stabilize within 1 ms. Code execution continues during this shift. There is no indication that the shift has occurred. OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency.
REGISTER 4-2:
OSCTUNE - OSCILLATOR TUNING RESISTOR (ADDRESS: 90h)
U-0 -- bit 7 U-0 -- U-0 -- R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0 bit 0
bit 7-5 bit 4-0
Unimplemented: Read as `0' TUN<4:0>: Frequency Tuning bits 01111 = Maximum frequency 01110 = * * * 00001 = 00000 = Center frequency. Oscillator module is running at the calibrated frequency. 11111 = * * * 10000 = Minimum frequency Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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4.4.3 LFINTOSC 4.4.5
The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated (approximate) 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 4-1). 31 kHz can be selected via software using the IRCF bits (see Section 4.4.4 "Frequency Select Bits (IRCF)"). The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF = 000) as the System Clock Source (SCS = 1), or when any of the following are enabled: * * * * * Two-Speed Start-up (IESO = 1 and IRCF = 000) Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM) Selected as LCD module clock source
HF AND LF INTOSC CLOCK SWITCH TIMING
When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power. If this is the case, there is a 10 s delay after the IRCF bits are modified before the frequency selection takes place. The LTS/HTS bits will reflect the current active status of the LFINTOSC and the HFINTOSC oscillators. The timing of a frequency selection is as follows: 1. 2. 3. 4. 5. 6. IRCF bits are modified. If the new clock is shut down, a 10 s clock start-up delay is started. Clock switch circuitry waits for a falling edge of the current clock. CLKO is held low and the clock switch circuitry waits for a rising edge in the new clock. CLKO is now connected with the new clock. HTS/LTS bits are updated as required. Clock switch is complete.
The LF Internal Oscillator (LTS) bit (OSCCON<1>) indicates whether the LFINTOSC is stable or not.
4.4.4
FREQUENCY SELECT BITS (IRCF)
The output of the 8 MHz HFINTOSC and 31 kHz LFINTOSC connect to a postscaler and multiplexer (see Figure 4-1). The Internal Oscillator Frequency select bits, IRCF<2:0> (OSCCON<6:4>), select the frequency output of the internal oscillators. One of eight frequencies can be selected via software: * * * * * * * * 8 MHz 4 MHz (Default after Reset) 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 31 kHz Note: Following any Reset, the IRCF bits are set to `110' and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency.
If the internal oscillator speed selected is between 8 MHz and 125 kHz, there is no start-up delay before the new frequency is selected. This is because the old and the new frequencies are derived from the HFINTOSC via the postscaler and multiplexer.
4.5
Clock Switching
The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bit.
4.5.1
SYSTEM CLOCK SELECT (SCS) BIT
The System Clock Select (SCS) bit (OSCCON<0>) selects the system clock source that is used for the CPU and peripherals. * When SCS = 0, the system clock source is determined by configuration of the FOSC<2:0> bits in the Configuration Word register (CONFIG). * When SCS = 1, the system clock source is chosen by the internal oscillator frequency selected by the IRCF bits. After a Reset, SCS is always cleared. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bit. The user can monitor the OSTS (OSCCON<3>) to determine the current system clock source.
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4.5.2 OSCILLATOR START-UP TIME-OUT STATUS BIT 4.6.2
1. 2.
TWO-SPEED START-UP SEQUENCE
The Oscillator Start-up Time-out Status (OSTS) bit (OSCCON<3>) indicates whether the system clock is running from the external clock source, as defined by the FOSC bits, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes.
3. 4. 5. 6. 7.
4.6
Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC as the clock source and go back to Sleep without waiting for the primary oscillator to become stable. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit (OSCCON<3>) to remain clear.
Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF bits (OSCCON<6:4>). OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source.
4.6.3
CHECKING EXTERNAL/INTERNAL CLOCK STATUS
Checking the state of the OSTS bit (OSCCON<3>) will confirm if the PIC16F917/916/914/913 is running from the external clock source as defined by the FOSC bits in the Configuration Word (CONFIG) or the internal oscillator.
When the PIC16F917/916/914/913 is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) is enabled (see Section 4.3.1 "Oscillator Start-up Timer (OST)"). The OST timer will suspend program execution until 1024 oscillations are counted. Two-Speed Start-up mode minimizes the delay in code execution by operating from the internal oscillator as the OST is counting. When the OST count reaches 1024 and the OSTS bit (OSCCON<3>) is set, program execution switches to the external oscillator.
4.6.1
TWO-SPEED START-UP MODE CONFIGURATION
Two-Speed Start-up mode is configured by the following settings: * IESO = 1 (CONFIG<10>) Internal/External Switchover bit. * SCS = 0. * FOSC configured for LP, XT or HS mode. Two-Speed Start-up mode is entered after: * Power-on Reset (POR) and, if enabled, after PWRT has expired, or * Wake-up from Sleep. If the external clock oscillator is configured to be anything other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep.
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FIGURE 4-7: TWO-SPEED START-UP
Q1 INTOSC T TOST OSC1 0 1 1022 1023 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
OSC2 Program Counter PC PC + 1 PC + 2
System Clock
4.7
Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) is designed to allow the device to continue to operate in the event of an oscillator failure. The FSCM can detect oscillator failure at any point after the device has exited a Reset or Sleep condition and the Oscillator Start-up Timer (OST) has expired.
The frequency of the internal oscillator will depend upon the value contained in the IRCF bits (OSCCON<6:4>). Upon entering the Fail-Safe condition, the OSTS bit (OSCCON<3>) is automatically cleared to reflect that the internal oscillator is active and the WDT is cleared. The SCS bit (OSCCON<0>) is not updated. Enabling FSCM does not affect the LTS bit. The FSCM sample clock is generated by dividing the INTOSC clock by 64. This will allow enough time between FSCM sample clocks for a system clock edge to occur. Figure 4-8 shows the FSCM block diagram. On the rising edge of the sample clock, a monitoring latch (CM = 0) will be cleared. On a falling edge of the primary system clock, the monitoring latch will be set (CM = 1). In the event that a falling edge of the sample clock occurs, and the monitoring latch is not set, a clock failure has been detected. The assigned internal oscillator is enabled when FSCM is enabled as reflected by the IRCF. Note 1: Two-Speed Start-up is automatically enabled when the Fail-Safe Clock Monitor mode is enabled.
FIGURE 4-8:
FSCM BLOCK DIAGRAM
Primary Clock
LFINTOSC Oscillator
Clock Fail Detector / 64
Clock Failure Detected
The FSCM function is enabled by setting the FCMEN bit in the Configuration Word (CONFIG). It is applicable to all external clock options (LP, XT, HS, EC or RC modes). In the event of an external clock failure, the FSCM will set the OSFIF bit (PIR2<7>) and generate an oscillator fail interrupt if the OSFIE bit (PIE2<7>) is set. The device will then switch the system clock to the internal oscillator. The system clock will continue to come from the internal oscillator unless the external clock recovers and the Fail-Safe condition is exited.
2: Primary clocks with a frequency ~488 Hz will be considered failed by the FSCM. A slow starting oscillator can cause an FSCM interrupt.
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4.7.1 FAIL-SAFE CONDITION CLEARING
The Fail-Safe condition is cleared after a Reset, the execution of a SLEEP instruction, or a modification of the SCS bit. While in Fail-Safe condition, the PIC16F91X uses the internal oscillator as the system without exiting the Fail-Safe condition. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared.
FIGURE 4-9:
Sample Clock System Clock Output CM Output (Q)
FSCM TIMING DIAGRAM
Oscillator Failure
Failure Detected OSCFIF
CM Test Note:
CM Test
CM Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
4.7.2
RESET OR WAKE-UP FROM SLEEP
Note: Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit (OSCCON<3>) to verify the oscillator start-up and system clock switchover has successfully completed.
The FSCM is designed to detect oscillator failure at any point after the device has exited a Reset or Sleep condition and the Oscillator Start-up Timer (OST) has expired. If the external clock is EC or RC mode, monitoring will begin immediately following these events. For LP, XT or HS mode the external oscillator may require a start-up time considerably longer than the FSCM sample clock time, a false clock failure may be detected (see Figure 4-9). To prevent this, the internal oscillator is automatically configured as the system clock and functions until the external clock is stable (the OST has timed out). This is identical to Two-Speed Start-up mode. Once the external oscillator is stable, the LFINTOSC returns to its role as the FSCM source.
TABLE 4-2:
Addr 8Fh 90h 2007h(1) Legend: Note 1: 2: Name
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Bit 7 -- -- CPD Bit 6 IRCF2 -- CP Bit 5 IRCF1 -- Bit 4 IRCF0 TUN4 Bit 3 OSTS(2) TUN3 WDTE Bit 2 HTS TUN2 FOSC2 Bit 1 LTS TUN1 FOSC1 Bit 0 SCS TUN0 FOSC0 Value on: POR, BOR Value on all other Resets
OSCCON OSCTUNE CONFIG
-110 q000 -110 x000 ---0 0000 ---u uuuu -- --
MCLRE PWRTE
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by oscillators. See Register 16-1 for operation of all Configuration Word bits. See Register 4-1 for details.
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5.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock Counter mode is selected by setting the T0CS bit (OPTION_REG<5>). In this mode, the Timer0 module will increment either on every rising or falling edge of pin RA4/C1OUT/T0CKI/SEG4. The incrementing edge is determined by the source edge (T0SE) control bit (OPTION_REG<4>). Clearing the T0SE bit selects the rising edge. Note: Counter mode has specific external clock requirements. Additional information on these requirements is available in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023).
Figure 5-1 is a block diagram of the Timer0 module and the prescaler shared with the WDT. Note: Additional information on the Timer0 module is available in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023).
5.2
Timer0 Interrupt
5.1
Timer0 Operation
Timer mode is selected by clearing the T0CS bit (OPTION_REG<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.
A Timer0 interrupt is generated when the TMR0 register timer/counter overflows from FFh to 00h. This overflow sets the T0IF bit (INTCON<2>). The interrupt can be masked by clearing the T0IE bit (INTCON<5>). The T0IF bit must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The Timer0 interrupt cannot wake the processor from Sleep, since the timer is shut off during Sleep.
FIGURE 5-1:
CLKO (= FOSC/4)
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 0 1 1 SYNC 2 Cycles 0 0 TMR0 8
T0CKI pin T0SE T0CS
8-bit Prescaler 1 8
Set Flag bit T0IF on Overflow PSA
WDTE SWDTEN
PSA
PS<2:0> 16-bit Prescaler 31 kHz INTOSC Watchdog Timer WDTPS<3:0> Note:
1 WDT Time-out 0
16 PSA
T0SE, T0CS, PSA and PS<2:0> are bits in the Option register; WDTPS<3:0> are bits in the WDTCON register.
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5.3 Using Timer0 with an External Clock
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2 TOSC (and a small RC delay of 20 ns) and low for at least 2 TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device.
REGISTER 5-1:
OPTION_REG - OPTION REGISTER (ADDRESS: 81h OR 181h)
R/W-1 RBPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
bit 7
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values in WPUA register INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT/SEG0 pin 0 = Interrupt on falling edge of RB0/INT/SEG0 pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/C1OUT/T0CKI/SEG4 pin 0 = Internal instruction cycle clock (CLKO) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/C1OUT/T0CKI/SEG4 pin 0 = Increment on low-to-high transition on RA4/C1OUT/T0CKI/SEG4 pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate WDT Rate(1) 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1: A dedicated 16-bit WDT postscaler is available for the PIC16F917/916/914/913. See Section 16.6 "Watchdog Timer (WDT)" for more information. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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5.4 Prescaler
EXAMPLE 5-1:
BCF STATUS,RP0 CLRWDT CLRF TMR0 BSF STATUS,RP0
An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer. For simplicity, this counter will be referred to as "prescaler" throughout this data sheet. The prescaler assignment is controlled in software by the control bit PSA (OPTION_REG<3>). Clearing the PSA bit will assign the prescaler to Timer0. Prescale values are selectable via the PS<2:0> bits (OPTION_REG<2:0>). The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1, x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer.
CHANGING PRESCALER (TIMER0 WDT)
;Bank 0 ;Clear WDT ;Clear TMR0 and ; prescaler ;Bank 1 ;Required if desired ; PS2:PS0 is ; 000 or 001 ; ;Set postscaler to ; desired WDT rate ;Bank 0
MOVLW b'00101111' MOVWF OPTION_REG CLRWDT MOVLW MOVWF BCF b'00101xxx' OPTION_REG STATUS,RP0
5.4.1
SWITCHING PRESCALER ASSIGNMENT
To change prescaler from the WDT to the TMR0 module, use the sequence shown in Example 5-2. This precaution must be taken even if the WDT is disabled.
The prescaler assignment is fully under software control (i.e., it can be changed "on-the-fly" during program execution). To avoid an unintended device Reset, the following instruction sequence (Example 5-1 and Example 5-2) must be executed when changing the prescaler assignment from Timer0 to WDT.
EXAMPLE 5-2:
CLRWDT BSF MOVLW STATUS,RP0
CHANGING PRESCALER (WDT TIMER0)
;Clear WDT and ; prescaler ;Bank 1 ;Select TMR0, ; prescale, and ; clock source ; ;Bank 0
b'xxxx0xxx'
MOVWF BCF
OPTION_REG STATUS,RP0
TABLE 5-1:
Address 01h
REGISTERS ASSOCIATED WITH TIMER0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx INTE T0SE TRISA4 RBIE PSA TRISA3 T0IF PS2 TRISA2 INTF PS1 TRISA1 RBIF PS0 TRISA0 0000 000x 1111 1111 1111 1111 Value on all other Resets uuuu uuuu 0000 000x 1111 1111 1111 1111
TMR0
Timer0 Module Register GIE RBPU TRISA7 PEIE INTEDG TRISA6 T0IE T0CS TRISA5
0Bh/10Bh INTCON 81h 85h Legend: OPTION_REG TRISA
- = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.
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NOTES:
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6.0 TIMER1 MODULE WITH GATE CONTROL
The Timer1 Control register (T1CON), shown in Register 6-1, is used to enable/disable Timer1 and select the various features of the Timer1 module. Note: Additional information on timer modules is available in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023).
The PIC16F917/916/914/913 has a 16-bit timer. Figure 6-1 shows the basic block diagram of the Timer1 module. Timer1 has the following features: 16-bit timer/counter (TMR1H:TMR1L) Readable and writable Internal or external clock selection Synchronous or asynchronous operation Interrupt-on-overflow from FFFFh to 0000h Wake-up upon overflow (Asynchronous mode) Optional external enable input: - Selectable gate source: T1G or C2 output (T1GSS) - Selectable gate polarity (T1GINV) * Optional LP oscillator * * * * * * *
FIGURE 6-1:
TIMER1 ON THE PIC16F917/916/914/913 BLOCK DIAGRAM
TMR1ON T1GE Clear on special event trigger TMR1ON T1GE To C2 Comparator Module TMR1 Clock 0 TMR1H LP OSC
(2)
T1GINV
Set Flag bit TMR1IF on Overflow
TMR1(1) TMR1L
Synchronized Clock Input
1 1 FOSC/4 Internal Clock T1SYNC 1 Prescaler 1, 2, 4, 8 0 2 T1CKPS<1:0> Sleep Input Synchronize det
OSC1/T1OSI
0 OSC2/T1OSO FOSC = 000 FOSC = x00 T1OSCEN RC5/T1CKI/ CCP1/SEG10
T1CS
RC4/T1G/ SDO/SEG11 C2OUT
1
0 T1GSS
Note 1: 2:
Timer1 increments on the rising edge. ST Buffer is low-power type when using LP oscillator or high-speed type when using T1CKI.
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6.1 Timer1 Modes of Operation 6.3 Timer1 Prescaler
Timer1 can operate in one of three modes: * 16-bit timer with prescaler * 16-bit synchronous counter * 16-bit asynchronous counter In Timer mode, Timer1 is incremented on every instruction cycle. In Counter mode, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. In the Timer1 module, the module clock can be gated by the Timer1 gate, which can be selected as either the T1G pin or Comparator 2 output. If an external clock oscillator is needed (and the microcontroller is using the INTOSC without CLKO), Timer1 can use the LP oscillator as a clock source. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge. Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits (T1CON<5:4>) control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L.
6.4
Timer1 Gate
Timer1 gate source is software configurable to be the T1G pin or the output of Comparator 2. This allows the device to directly time external events using T1G or analog events using Comparator 2. See CMCON1 (Register 8-2) for selecting the Timer1 gate source. This feature can simplify the software for a Delta-Sigma A/D converter and many other applications. For more information on Delta-Sigma A/D converters, see the Microchip web site (www.microchip.com). Note: T1GE bit (T1CON<6>) must be set to use either T1G or C2OUT as the Timer1 gate source. See Register 8-2 for more information on selecting the Timer1 gate source.
6.2
Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 Interrupt Flag bit (PIR1<0>) is set. To enable the interrupt on rollover, you must set these bits: * Timer1 Interrupt Enable bit (PIE1<0>) * PEIE bit (INTCON<6>) * GIE bit (INTCON<7>) The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: The TMR1H:TTMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts.
Timer1 gate can be inverted using the T1GINV bit (T1CON<7>), whether it originates from the T1G pin or Comparator 2 output. This configures Timer1 to measure either the active-high or active-low time between events.
FIGURE 6-2:
T1CKI = 1 when TMR1 Enabled
TIMER1 INCREMENTING EDGE
T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
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REGISTER 6-1: T1CON - TIMER1 CONTROL REGISTER (ADDRESS: 10h)
R/W-0 T1GINV bit 7 bit 7 T1GINV: Timer1 Gate Invert bit(1) 1 = Timer1 gate is inverted 0 = Timer1 gate is not inverted T1GE: Timer1 Gate Enable bit(2) If TMR1ON = 0: This bit is ignored. If TMR1ON = 1: 1 = Timer1 gate is enabled 0 = Timer1 gate is disabled T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value T1OSCEN: LP Oscillator Enable Control bit If INTOSC without CLKO oscillator is active: 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off Else: This bit is ignored. T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from RC5/T1CKI/CCP1/SEG10 pin or T1OSC (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: T1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit (CMCON1<1>), as a Timer1 gate source. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 T1GE R/W-0 R/W-0 R/W-0 R/W-0 T1SYNC R/W-0 TMR1CS R/W-0 TMR1ON bit 0 T1CKPS1 T1CKPS0 T1OSCEN
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
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6.5 Timer1 Operation in Asynchronous Counter Mode 6.6 TIMER1 OSCILLATOR
To minimize the multiplexing of peripherals on the I/O ports, the dedicated TMR1 oscillator, which is normally used for TMR1 real-time clock applications, is eliminated. Instead, the TMR1 module can enable the LP oscillator. If the microcontroller is programmed to run from INTOSC with no CLKO or LP oscillator: 1. Setting the T1OSCEN and TMR1CS bits to `1' will enable the LP oscillator to clock TMR1 while the microcontroller is clocked from either the INTOSC or LP oscillator. Note that the T1OSC and LP oscillators share the same circuitry. Therefore, when LP oscillator is selected and T1OSC is enabled, both the microcontroller and the Timer1 module share the same clock source. Sleep mode does not shut off the LP oscillator operation (i.e., if the INTOSC oscillator runs the microcontroller, and T1OSCEN = 1 (TMR1 is running from the LP oscillator), then the LP oscillator will continue to run during Sleep mode.
If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt-on-overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 6.5.1 "Reading and Writing Timer1 in Asynchronous Counter Mode"). Note: The ANSEL (91h) and CMCON0 (9Ch) registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
6.5.1
READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE
2.
Reading TMR1H or TMR1L, while the timer is running from an external asynchronous clock, will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the timer register. Reading the 16-bit value requires some care. Examples in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023) show how to read and write Timer1 when it is running in Asynchronous mode.
In all oscillator modes except for INTOSC with no CLKOUT and LP, the T1OSC enable option is unavailable and is ignored. Note: When INTOSC without CLKO oscillator is selected and T1OSCEN = 1, the LP oscillator will run continuously independent of the TMR1ON bit.
6.7
Resetting Timer1 Using a CCP Trigger Output
If the CCP1 or CCP2 module is configured in Compare mode to generate a "special event trigger" (CCP1M<3:0> = 1011), this signal will reset Timer1. Note: The special event triggers from the CCP1 and CCP2 modules will not set interrupt flag bit, TMR1IF (PIR1<0>).
Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1 or CCP2, the write will take precedence. In this mode of operation, the CCPRxH:CCPRxL register pair effectively becomes the period register for Timer1.
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6.8 Resetting of Timer1 Register Pair (TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a POR, or any other Reset, except by the CCP1 and CCP2 special event triggers. T1CON register is reset to 00h on a Power-on Reset, or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other Resets, the register is unaffected.
6.9
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: * Timer1 must be on (T1CON<0>) * TMR1IE bit (PIE1<0>) must be set * PEIE bit (INTCON<6>) must be set The device will wake-up on an overflow. If the GIE bit (INTCON<7>) is set, the device will wake-up and jump to the Interrupt Service Routine (0004h) on an overflow. If the GIE bit is clear, execution will continue with the next instruction.
TABLE 6-1:
Addr 0Bh/ 8Bh 0Ch 0Eh 0Fh 10h 1Ah 8Ch Name INTCON PIR1 TMR1L TMR1H T1CON CMCON1 PIE1
REGISTERS ASSOCIATED WITH TIMER1
Bit 7 GIE EEIF Bit 6 PEIE ADIF Bit 5 T0IE RCIF Bit 4 INTE TXIF Bit 3 RBIE SSPIF Bit 2 T0IF CCP1IF Bit 1 INTF TMR2IF Bit 0 RBIF Value on POR, BOR Value on all other Resets
0000 000x 0000 000x
TMR1IF 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register T1GINV -- EEIE T1GE -- ADIE -- RCIE -- TXIE -- SSPIE -- CCP1IE T1GSS TMR2IE
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu C2SYNC ---- --10 ---- --10 TMR1IE 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module.
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7.0
* * * * * *
TIMER2 MODULE
7.1
Timer2 Operation
The Timer2 module timer has the following features: 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match with PR2
Timer2 has a control register shown in Register 7-1. TMR2 can be shut-off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. Figure 7-1 is a simplified block diagram of the Timer2 module. The prescaler and postscaler selection of Timer2 are controlled by this register.
Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPSx (T2CON<1:0>). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)). The prescaler and postscaler counters are cleared when any of the following occurs: * A write to the TMR2 register * A write to the T2CON register * Any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset) TMR2 is not cleared when T2CON is written.
REGISTER 7-1:
T2CON - TIMER2 CONTROL REGISTER (ADDRESS: 12h)
U-0 -- bit 7 R/W-0 TOUTPS3 R/W-0 TOUTPS2 R/W-0 TOUTPS1 R/W-0 TOUTPS0 R/W-0 R/W-0 R/W-0 T2CKPS0 bit 0 TMR2ON T2CKPS1
bit 7 bit 6-3
Unimplemented: Read as `0' TOUTPS<3:0>: Timer2 Output Postscale Select bits 0000 =1:1 Postscale 0001 =1:2 Postscale * * * 1111 =1:16 Postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 =Prescaler is 1 01 =Prescaler is 4 1x =Prescaler is 16 Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 2
bit 1-0
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7.2 Timer2 Interrupt 7.3 Timer2 Output
The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. The output of TMR2 (before the postscaler) is fed to the SSP module, which optionally uses it to generate the shift clock.
FIGURE 7-1:
TIMER2 BLOCK DIAGRAM
TMR2 Output(1) Sets Flag bit TMR2IF
FOSC/4
Prescaler 1:1, 1:4, 1:16 2 T2CKPS<1:0>
TMR2 Comparator
Reset
EQ PR2
Postscaler 1:1 to 1:16 4 TOUTPS<3:0>
Note 1: TMR2 register output can be software selected by the SSP module as a baud clock.
TABLE 7-1:
Addr 0Bh/ 8Bh 0Ch 11h 12h 8Ch 92h Name INTCON PIR1 TMR2 T2CON PIE1 PR2
REGISTERS ASSOCIATED WITH TIMER2
Bit 7 GIE EEIF Bit 6 PEIE ADIF Bit 5 T0IE RCIF Bit 4 INTE TXIF Bit 3 RBIE SSPIF Bit 2 T0IF CCP1IF Bit 1 INTF TMR2IF Bit 0 RBIF TMR1IF Value on POR, BOR Value on all other Resets
0000 000x 0000 000x 0000 0000 0000 0000 0000 0000 0000 0000
Holding Register for the 8-bit TMR2 Register -- EEIE
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 1111 1111 1111 1111
Timer2 Period Register
Legend:
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the Timer2 module.
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NOTES:
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8.0 COMPARATOR MODULE
The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with I/O port pins RA<3:0>, while the outputs are multiplexed to pins RA<5:4>. An on-chip Comparator Voltage Reference (CVREF) can also be applied to the inputs of the comparators. The CMCON0 register (Register 8-1) controls the comparator input and output multiplexers. A block diagram of the various comparator configurations is shown in Figure 8-3.
REGISTER 8-1:
CMCON0 - COMPARATOR CONFIGURATION REGISTER (ADDRESS: 9Ch)
R-0 C2OUT bit 7 R-0 C1OUT R/W-0 C2INV R/W-0 C1INV R/W-0 CIS R/W-0 CM2 R/W-0 CM1 R/W-0 CM0 bit 0
bit 7
C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1: 0 = C2 VIN+ > C2 VIN1 = C2 VIN+ < C2 VINC1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1: 0 = C1 VIN+ > C1 VIN1 = C1 VIN+ < C1 VINC2INV: Comparator 2 Output Inversion bit 1 = C2 Output inverted 0 = C2 Output not inverted C1INV: Comparator 1 Output Inversion bit 1 = C1 Output inverted 0 = C1 Output not inverted CIS: Comparator Input Switch bit When CM<2:0> = 010: 1 = C1 VIN- connects to RA3/AN3/C1+/VREF+/SEG15 C2 VIN- connects to RA2/AN2/C2+/VREF-/COM2 0 = C1 VIN- connects to RA0/AN0/C1-/SEG12 C2 VIN- connects to RA1/AN1/C2-/SEG7 When CM<2:0> = 001: 1 = C1 VIN- connects to RA3/AN3/C1+/VREF+/SEG15 0 = C1 VIN- connects to RA0/AN0/C1-/SEG12 When CM<2:0> = 101: 1 = C2 VIN+ connects to internal 0.6V reference 0 = C2 VIN+ connects to RA2/AN2/C2+/VREF-/COM2 CM<2:0>: Comparator Mode bits(1) See Figure 8-3 for comparator modes and CM<2:0> bit settings. Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2-0
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8.1 Comparator Operation
FIGURE 8-1:
VIN+ VIN-
SINGLE COMPARATOR
+ -
A single comparator is shown in Figure 8-1 along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 8-1 represent the uncertainty due to input offsets and response time. Note: To use CIN+ and CIN- pins as analog inputs, the appropriate bits must be programmed in the CMCON0 (9Ch) register.
Output
VINVIN- VIN+ VIN+
Output Output
The polarity of the comparator output can be inverted by setting the CxINV bits (CMCON0<5:4>). Clearing CxINV results in a non-inverted output. A complete table showing the output state versus input conditions and the polarity bit is shown in Table 8-1.
8.2
Analog Input Connection Considerations
TABLE 8-1:
OUTPUT STATE VS. INPUT CONDITIONS
CINV 0 0 1 1 CxOUT 0 1 1 0
Input Conditions VIN- > VIN+ VIN- < VIN+ VIN- > VIN+ VIN- < VIN+
A simplified circuit for an analog input is shown in Figure 8-2. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage.
FIGURE 8-2:
ANALOG INPUT MODEL
VDD Rs < 10K AIN VT = 0.6V RIC
VA
CPIN 5 pF
VT = 0.6V
Leakage 500 nA
Vss
Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE= Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage
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8.3 Comparator Configuration
There are eight modes of operation for the comparators. The CMCON0 register is used to select these modes. Figure 8-3 shows the eight possible modes. If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Section 19.0 "Electrical Specifications". Note: Comparator interrupts should be disabled during a Comparator mode change. Otherwise, a false interrupt may occur.
FIGURE 8-3:
COMPARATOR I/O OPERATING MODES
Comparators Off CM<2:0> = 111 D RA0/AN0/ C1-/SEG12 D RA3/AN3/ C1+/VREF+/SEG15 RA1/AN1/ D C2-/SEG7 D RA2/AN2/ C2+/VREF-/COM2 VINVIN+ C1 Off (Read as `0')
Comparators Reset (POR Default Value) CM<2:0> = 000 RA0/AN0/ A VINC1-/SEG12 C1 Off (Read as `0') VIN+ A RA3/AN3/ C1+/VREF+/SEG15 RA1/AN1/ A C2-/SEG7 A RA2/AN2/ C2+/VREF-/COM2 VINVIN+ C2 Off (Read as `0')
VINVIN+ C2 Off (Read as `0')
Two Independent Comparators CM<2:0> = 100 RA0/AN0/ A C1-/SEG12 A RA3/AN3/ C1+/VREF+/SEG15 RA1/AN1/ A C2-/SEG7 A RA2/AN2/ C2+/VREF-/COM2 VINVIN+ C1 C1OUT
Four Inputs Multiplexed to Two Comparators CM<2:0> = 010 RA0/AN0/ A C1-/SEG12 CIS = 0 VINA CIS = 1 RA3/AN3/ C1 VIN+ C1+/VREF+/SEG15 A RA1/AN1/ C2-/SEG7 A RA2/AN2/ C2+/VREF-/COM2 CIS = 0 CIS = 1 VINVIN+ C2
C1OUT
VINVIN+ C2 C2OUT
C2OUT
From CVREF Module Two Common Reference Comparators with Outputs CM<2:0> = 110 RA0/AN0/ C1-/SEG12 A VINVIN+ C1 C1OUT RA4 VINVIN+ C2 C2OUT RA1/AN1/ C2-/SEG7 A VINVIN+ C2 C2OUT RA5
Two Common Reference Comparators CM<2:0> = 011 A RA0/AN0/ C1-/SEG12 D RA3/AN3/ C1+/VREF+/SEG15 RA1/AN1/ A C2-/SEG7 A RA2/AN2/ C2+/VREF-/COM2 VINVIN+ C1 C1OUT
A RA2/AN2/ C2+/VREF-/COM2
One Independent Comparator with Reference Option CM<2:0> = 101 RA0/AN0/ C1-/SEG12 RA3/AN3/ C1+/VREF+/ SEG15 RA1/AN1/ C2-/SEG7 RA2/AN2/ C2+/VREF-/ COM2 Legend: A = Analog Input, port reads zeros always. D D VINVIN+ C1 Off (Read as `0')
Three Inputs Multiplexed to Two Comparators CM<2:0> = 001 RA0/AN0/ A C1-/SEG12 A RA3/AN3/ C1+/VREF+/SEG15 RA1/AN1/ A C2-/SEG7 A RA2/AN2/ C2+/VREF-/COM2 CIS = 0 CIS = 1 VINVIN+ VINVIN+ C2 C2OUT C1 C1OUT
A A A CIS = 0 CIS = 1
VINVIN+ C2 C2OUT RA5
Internal 0.6V reference
D = Digital Input.
CIS (CMCON0<3>) is the computer Input Switch.
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FIGURE 8-4: COMPARATOR C1 OUTPUT BLOCK DIAGRAM
MULTIPLEX Port Pins
C1INV
To C1OUT pin To Data Bus Q EN RD CMCON D
Set C1IF bit
Q
D EN RD CMCON
CL
NReset
FIGURE 8-5:
COMPARATOR C2 OUTPUT BLOCK DIAGRAM
MULTIPLEX Port Pins C2SYNC To TMR1 0
C2INV
To C2OUT pin 1 Q EN D TMR1 Clock Source(1)
To Data Bus
Q EN RD CMCON
D
Set C2IF bit
Q
D EN
CL
RD CMCON
Reset Note 1: Comparator 2 output is latched on falling edge of T1 clock source.
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REGISTER 8-2: CMCON1 - COMPARATOR CONFIGURATION REGISTER (ADDRESS: 97h)
U-0 -- bit 7 bit 7-2: bit 1 Unimplemented: Read as `0' T1GSS: Timer1 Gate Source Select bit 1 = Timer1 gate source is T1G pin (RC4 must be configured as digital input) 0 = Timer1 gate source is Comparator 2 Output C2SYNC: Comparator 2 Synchronize bit 1 = C2 output synchronized with falling edge of Timer1 clock 0 = C2 output not synchronized with Timer1 clock Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 T1GSS R/W-0 C2SYNC bit 0
bit 0
8.4
Comparator Outputs
8.5
Comparator Interrupts
The comparator outputs are read through the CMCON0 register. These bits are read-only. The comparator outputs may also be directly output to the RA4 and RA5 I/O pins. When enabled, multiplexers in the output path of the RA4 and RA5 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. Figure 8-4 and Figure 8-5 show the output block diagram for Comparator 1 and 2. The TRIS bits will still function as an output enable/disable for the RA4 and RA5 pins while in this mode. The polarity of the comparator outputs can be changed using the C1INV and C2INV bits (CMCON0<5:4>). Timer1 gate source can be configured to use the T1G pin or Comparator 2 output as selected by the T1GSS bit (CMCON1<1>). This feature can be used to time the duration or interval of analog events. The output of Comparator 2 can also be synchronized with Timer1 by setting the C2SYNC bit (CMCON1<0>). When enabled, the output of Comparator 2 is latched on the falling edge of Timer1 clock source. If a prescaler is used with Timer1, Comparator 2 is latched after the prescaler. To prevent a race condition, the Comparator 2 output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See (Figure 8-5), Comparator 2 Block Diagram and (Figure 6-1), Timer1 Block Diagram for more information. It is recommended to synchronize Comparator 2 with Timer1 by setting the C2SYNC bit when Comparator 2 is used as the Timer1 gate source. This ensures Timer1 does not miss an increment if Comparator 2 changes during an increment.
The comparator interrupt flags are set whenever there is a change in the output value of its respective comparator. Software will need to maintain information about the status of the output bits, as read from CMCON0<7:6>, to determine the actual change that has occurred. The CxIF bits, PIR2<6:5>, are the Comparator Interrupt flags. This bit must be reset in software by clearing it to `0'. Since it is also possible to write a `1' to this register, a simulated interrupt may be initiated. The CxIE bits (PIE2<6:5>) and the PEIE bit (INTCON<6>) must be set to enable the interrupts. In addition, the GIE bit must also be set. If any of these bits are cleared, the interrupt is not enabled, though the CxIF bits will still be set if an interrupt condition occurs. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of CMCON0. This will end the mismatch condition. Clear flag bit CxIF
A mismatch condition will continue to set flag bit CxIF. Reading CMCON0 will end the mismatch condition and allow flag bits CxIF to be cleared. Note: If a change in the CMCON0 register (CxOUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CxIF (PIR2<6:5>) interrupt flag may not get set.
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8.6 Comparator Reference
8.6.2
The comparator module also allows the selection of an internally generated voltage reference for one of the comparator inputs. The VRCON register, Register 8-3, controls the voltage reference module shown in Figure 8-6.
VOLTAGE REFERENCE ACCURACY/ERROR
8.6.1
CONFIGURING THE VOLTAGE REFERENCE
The voltage reference can output 32 distinct voltage levels; 16 in a high range and 16 in a low range. The following equation determines the output voltages:
The full range of VSS to VDD cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 8-6) keep CVREF from approaching VSS or VDD. The exception is when the module is disabled by clearing the VREN bit (VRCON<7>). When disabled, the reference voltage is VSS when VR<3:0> = 0000. This allows the comparators to detect a zero-crossing and not consume CVREF module current. The voltage reference is VDD derived and therefore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the comparator voltage reference can be found in Section 19.0 "Electrical Specifications".
EQUATION 8-1:
VRR = 1 (low range): CVREF = (VR3:VR0/24) x VDD VRR = 0 (high range): CVREF = (VDD/4) + (VR3:VR0 x VDD/32)
FIGURE 8-6:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages 8R R R R R
VDD 8R 16-1 Analog MUX VREN CVREF to Comparator Input VRR
VR<3:0> VREN VR <3:0> = `0000' VRR
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8.7 Comparator Response Time 8.9 Effects of a Reset
Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output is ensured to have a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (Table 19-10). A device Reset forces the CMCON0, CMCON1 and VRCON registers to their Reset states. This forces the comparator module to be in the Comparator Reset mode, CM<2:0> = 000 and the voltage reference to its OFF state. Thus, all potential inputs are analog inputs with the comparator and voltage reference disabled to consume the smallest current possible.
8.8
Operation During Sleep
The comparators and voltage reference, if enabled before entering Sleep mode, remain active during Sleep. This results in higher Sleep currents than shown in the power-down specifications. The additional current consumed by the comparator and the voltage reference is shown separately in the specifications. To minimize power consumption while in Sleep mode, turn off the comparator, CM<2:0> = 111, and voltage reference, VRCON<7> = 0. While the comparator is enabled during Sleep, an interrupt will wake-up the device. If the GIE bit (INTCON<7>) is set, the device will jump to the interrupt vector (0004h), and if clear, continues execution with the next instruction. If the device wakes up from Sleep, the contents of the CMCON0, CMCON1 and VRCON registers are not affected.
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REGISTER 8-3: VRCON - VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 9Dh)
R/W-0 VREN bit 7 bit 7 VREN: CVREF Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down, no IDD drain and CVREF = VSS. Unimplemented: Read as `0' VRR: CVREF Range Selection bit 1 = Low range 0 = High range Unimplemented: Read as `0' VR<3:0>: CVREF value selection 0 VR<3:0> 15 When VRR = 1: CVREF = (VR<3:0>/24) * VDD When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 VRR R/W-0 -- R/W-0 VR3 R/W-0 VR2 R/W-0 VR1 R/W-0 VR0 bit 0
bit 6 bit 5
bit 4 bit 3-0
TABLE 8-2:
Address 0Bh/8Bh 0Dh 9Ch 97h 85h 8Dh 9Dh Legend: Name INTCON PIR2
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Bit 7 GIE OSFIF C2OUT -- TRISA7 OSFIE VREN Bit 6 PEIE C2IF C1OUT -- TRISA6 C2IE -- Bit 5 T0IE C1IF C2INV -- TRISA5 C1IE VRR Bit 4 INTE LCDIF C1INV -- TRISA4 LCDIE -- Bit 3 RBIE -- CIS -- TRISA3 -- VR3 Bit 2 T0IF LVDIF CM2 -- TRISA2 LVDIE VR2 Bit 1 INTF -- CM1 T1GSS TRISA1 -- VR1 Bit 0 RBIF CCP2IF CM0 C2SYNC TRISA0 CCP2IE VR0 Value on POR, BOR 0000 000x 0000 -0-0 0000 0000 ---- --10 1111 1111 0000 -0-0 0-0- 0000 Value on all other Resets 0000 000x 0000 -0-0 0000 0000 ---- --10 1111 1111 0000 -0-0 0-0- 0000
CMCON0 CMCON1 TRISA PIE2 VRCON
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the comparator or Comparator Voltage Reference module.
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9.0 LIQUID CRYSTAL DISPLAY (LCD) DRIVER MODULE
Once the module is initialized for the LCD panel, the individual bits of the LCDDATA<11:0> registers are cleared/set to represent a clear/dark pixel, respectively: * * * * * * * * * * * * LCDDATA0 LCDDATA1 LCDDATA2 LCDDATA3 LCDDATA4 LCDDATA5 LCDDATA6 LCDDATA7 LCDDATA8 LCDDATA9 LCDDATA10 LCDDATA11 SEG7COM0:SEG0COM0 SEG15COM0:SEG8COM0 SEG23COM0:SEG16COM0 SEG7COM1:SEG0COM1 SEG15COM1:SEG8COM1 SEG23COM1:SEG16COM1 SEG7COM2:SEG0COM2 SEG15COM2:SEG8COM2 SEG23COM2:SEG16COM2 SEG7COM3:SEG0COM3 SEG15COM3:SEG8COM3 SEG23COM3:SEG16COM3
The Liquid Crystal Display (LCD) driver module generates the timing control to drive a static or multiplexed LCD panel. In the PIC16F914/917 devices (PIC16F914/917), the module drives the panels of up to four commons and up to 24 segments and in the PIC16F913/916 devices (PIC16F913/916), the module drives the panels of up to four commons and up to 16 segments. It also provides control of the LCD pixel data. The LCD driver module supports: * Direct driving of LCD panel * Three LCD clock sources with selectable prescaler * Up to four commons: - Static - 1/2 multiplex - 1/3 multiplex - 1/4 multiplex * Up to 24 (in PIC16F914/917 devices)/16 (in PIC16F913/916 devices) segments * Static, 1/2 or 1/3 LCD Bias The module has 32 registers: * LCD Control Register (LCDCON) * LCD Phase Register (LCDPS) * Three LCD Segment Enable Registers (LCDSE<2:0>) * 24 LCD Data Registers (LCDDATA<11:0>) The LCDCON register, shown in Register 9-1, controls the operation of the LCD driver module. The LCDPS register, shown in Register 9-2, configures the LCD clock source prescaler and the type of waveform; Type-A or Type-B. The LCDSE<2:0> registers configure the functions of the port pins: * LCDSE0 * LCDSE1 * LCDSE2 SE<7:0> SE<15:8> SE<23:16>
As an example, LCDDATAx is detailed in Register 9-4. Once the module is configured, the LCDEN (LCDCON<7>) bit is used to enable or disable the LCD module. The LCD panel can also operate during Sleep by clearing the SLPEN (LCDCON<6>) bit. Note: Writing into the registers LCDDATA2, LCDDATA5, LCDDATA8 and LCDDATA11 in PIC16F913/916 devices will not affect the status of any pixel and these registers can be used as General Purpose Registers.
As an example, LCDSEn is detailed in Register 9-3. Note: The LCDSE2 register is not implemented in PIC16F913/916 devices.
(c) 2005 Microchip Technology Inc.
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FIGURE 9-1: LCD DRIVER MODULE BLOCK DIAGRAM
Data Bus
LCDDATAx Registers 12 x 8 (= 4 x 24)
96 to 24 MUX
SEG<23:0> To I/O Pads(1)
Timing Control LCDCON LCDPS LCDSEn COM<3:0> To I/O Pads(1)
FOSC/8192 T10SC/32 LFINTOSC/32 Clock Source Select and Prescaler
Note 1:
These are not directly connected to the I/O pads. See Section 3.0 "I/O Ports" for more detail.
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REGISTER 9-1: LCDCON - LIQUID CRYSTAL DISPLAY CONTROL REGISTER (ADDRESS: 107h)
R/W-0 LCDEN bit 7 bit 7 LCDEN: LCD Driver Enable bit 1 = LCD driver module is enabled 0 = LCD driver module is disabled SLPEN: LCD Driver Enable in Sleep mode bit 1 = LCD driver module is disabled in Sleep mode 0 = LCD driver module is enabled in Sleep mode WERR: LCD Write Failed Error bit 1 = LCDDATAx register written while LCDPS = 0 (must be cleared in software) 0 = No LCD write error VLCDEN: LCD Bias Voltage Pins Enable bit 1 = VLCD pins are enabled 0 = VLCD pins are disabled CS<1:0>: Clock Source Select bits 00 = FOSC/8192 01 = T1OSC (Timer1)/32 1x = LFINTOSC (31 kHz)/32 LMUX<1:0>: Commons Select bits LMUX<1:0> 00 01 10 11 Note 1: Multiplex Static (COM0) 1/2 (COM<1:0>) 1/3 (COM<2:0>) 1/4 (COM<3:0>) Maximum Maximum Number of Pixels Number of Pixels (PIC16F913/916) (PIC16F914/917) 16 32 48 60(1) 24 48 72 96 Bias Static 1/2 or 1/3 1/2 or 1/3 1/3 R/W-0 SLPEN R/C-0 WERR R/W-1 VLCDEN R/W-0 CS1 R/W-0 CS0 R/W-1 LMUX1 R/W-1 LMUX0 bit 0
bit 6
bit 5
bit 4
bit 3-2
bit 1-0
On PIC16F913/916 devices, COM3 and SEG15 are shared on one pin, limiting the device from driving 64 pixels.
Legend: R = Readable bit C = Only clearable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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REGISTER 9-2: LCDPS - LCD PRESCALER SELECT REGISTER (ADDRESS: 108h)
R/W-0 WFT bit 7 bit 7 WFT: Waveform Type Select bit 1 = Type-B waveform (phase changes on each frame boundary) 0 = Type-A waveform (phase changes within each common type) BIASMD: Bias Mode Select bit When LMUX<1:0> = 00: 0 = Static Bias mode (do not set this bit to `1') When LMUX<1:0> = 01: 1 = 1/2 Bias mode 0 = 1/3 Bias mode When LMUX<1:0> = 10: 1 = 1/2 Bias mode 0 = 1/3 Bias mode When LMUX<1:0> = 11: 0 = 1/3 Bias mode (do not set this bit to `1') LCDA: LCD Active Status bit 1 = LCD driver module is active 0 = LCD driver module is inactive WA: LCD Write Allow Status bit 1 = Write into the LCDDATAx registers is allowed 0 = Write into the LCDDATAx registers is not allowed LP<3:0>: LCD Prescaler Select bits 1111 = 1:16 1110 = 1:15 1101 = 1:14 1100 = 1:13 1011 = 1:12 1010 = 1:11 1001 = 1:10 1000 = 1:9 0111 = 1:8 0110 = 1:7 0101 = 1:6 0100 = 1:5 0011 = 1:4 0010 = 1:3 0001 = 1:2 0000 = 1:1 Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 BIASMD R-0 LCDA R-0 WA R/W-0 LP3 R/W-0 LP2 R/W-0 LP1 R/W-0 LP0 bit 0
bit 6
bit 5
bit 4
bit 3-0
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REGISTER 9-3: LCDSEn - LCD SEGMENT REGISTERS (ADDRESS: 11Ch, 11Dh OR 11Eh)
R/W-0 SEn bit 7 bit 7-0 SEn: Segment Enable bits 1 = Segment function of the pin is enabled 0 = I/O function of the pin is enabled Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 SEn R/W-0 SEn R/W-0 SEn R/W-0 SEn R/W-0 SEn R/W-0 SEn R/W-0 SEn bit 0
REGISTER 9-4:
LCDDATAx - LCD DATA REGISTERS (ADDRESS: 110h-119h, 11Ah, 11Bh)
R/W-0 SEGxCOMy bit 7 R/W-0 SEGxCOMy R/W-0 SEGxCOMy R/W-0 SEGxCOMy R/W-0 SEGxCOMy R/W-0 SEGxCOMy R/W-0 SEGxCOMy R/W-0 SEGxCOMy bit 0
bit 7-0
SEGx-COMy: Pixel On bits 1 = Pixel on (dark) 0 = Pixel off (clear) Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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9.1 LCD Clock Source Selection
9.1.1 LCD PRESCALER
The LCD driver module has 3 possible clock sources: * FOSC/8192 * T1OSC/32 * LFINTOSC/32 The first clock source is the system clock divided by 8192 (FOSC/8192). This divider ratio is chosen to provide about 1 kHz output when the system clock is 8 MHz. The divider is not programmable. Instead, the LCD prescaler bits, LCDPS<3:0>, are used to set the LCD frame clock rate. The second clock source is the T1OSC/32. This also gives about 1 kHz when a 32.768 kHz crystal is used with the Timer1 oscillator. To use the Timer1 oscillator as a clock source, the T1OSCEN (T1CON<3>) bit should be set. The third clock source is the 31 kHz LFINTOSC/32, which provides approximately 1 kHz output. The second and third clock sources may be used to continue running the LCD while the processor is in Sleep. Using the bits, CS<1:0> (LCDCON<3:2>), any of these clock sources can be selected. A 16-bit counter is available as a prescaler for the LCD clock. The prescaler is not directly readable or writable; its value is set by the LP<3:0> bits (LCDPS<3:0>), which determine the prescaler assignment and prescale ratio. The prescale values from 1:1 through 1:16.
9.2
LCD Bias Types
The LCD driver module can be configured into three bias types: * Static Bias (2 voltage levels: VSS and VDD) * 1/2 Bias (3 voltage levels: VSS, 1/2 VDD and VDD) * 1/3 Bias (4 voltage levels: VSS, 1/3 VDD, 2/3 VDD and VDD) This module uses an external resistor ladder to generate the LCD bias voltages. The external resistor ladder should be connected to the Bias 1 pin, Bias 2 pin, Bias 3 pin and VSS. The Bias 3 pin should also be connected to VDD. Figure 9-2 shows the proper way to connect the resistor ladder to the Bias pins. Note: VLCD pins used to supply LCD bias voltage are enabled on power-up (POR) and must be disabled by the user by clearing LCDCON<4>, the VLCDEN bit, (see Register 9-1).
FIGURE 9-2:
LCD BIAS RESISTOR LADDER CONNECTION DIAGRAM
Static Bias VLCD 0 VLCD 3 To VLCD 2 LCD VLCD 1 Driver VLCD 0(1) VLCD 1 VLCD 2 VLCD 3 VSS -- -- VDD 1/2 Bias 1/3 Bias VSS 1/2 VDD 1/2 VDD VDD VSS 1/3 VDD 2/3 VDD VDD
LCD Bias 3 VDD* VDD* 10 k*
LCD Bias 2
LCD Bias 1
Connections for External R-ladder Static Bias 1/2 Bias VSS
10 k*
VDD*
10 k*
10 k*
10 k* VSS
1/3 Bias
* Note 1:
These values are provided for design guidance only and should be optimized for the application by the designer. Internal connection.
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9.3 LCD Multiplex Types 9.6 LCD Frame Frequency
The LCD driver module can be configured into four multiplex types: * * * * Static (only COM0 used) 1/2 multiplex (COM0 and COM1 are used) 1/3 multiplex (COM0, COM1 and COM2 are used) 1/4 multiplex (all COM0, COM1, COM2 and COM3 are used) The rate at which the COM and SEG outputs change is called the LCD frame frequency.
TABLE 9-2:
Multiplex Static 1/2 1/3 1/4 Note:
FRAME FREQUENCY FORMULAS
Frame Frequency = Clock source/(4 x 1 x (LP<3:0> + 1)) Clock source/(2 x 2 x (LP<3:0> + 1)) Clock source/(1 x 3 x (LP<3:0> + 1)) Clock source/(1 x 4 x (LP<3:0> + 1))
The LMUX<1:0> setting decides the function of RB5, RA2 or either RA3 or RD0 pins (see Table 9-1 for details). If the pin is a digital I/O, the corresponding TRIS bit controls the data direction. If the pin is a COM drive, then the TRIS setting of that pin is overridden. Note: On a Power-on Reset, the LMUX<1:0> bits are `11'.
Clock source is FOSC/8192, T1OSC/32 or LFINTOSC/32.
TABLE 9-3:
TABLE 9-1:
LMUX <1:0> 00 01 10 11 Note 1:
RA3, RA2, RB5 FUNCTION
RA2 Digital I/O Digital I/O RB5 Digital I/O COM1 Driver LP<3:0> 2 3 4 5 6 7
APPROXIMATE FRAME FREQUENCY (IN Hz) USING FOSC @ 8 MHz, TIMER1 @ 32.768 kHz OR INTOSC
Static 85 64 51 43 37 32 1/2 85 64 51 43 37 32 1/3 114 85 68 57 49 43 1/4 85 64 51 43 37 32
RA3/RD0(1) Digital I/O Digital I/O Digital I/O
COM2 Driver COM1 Driver
COM3 Driver COM2 Driver COM1 Driver RA3 for PIC16F913/916, RD0 for PIC16F914/917
9.4
Segment Enables
The LCDSEn registers are used to select the pin function for each segment pin. The selection allows each pin to operate as either an LCD segment driver or as one of the pin's alternate functions. To configure the pin as a segment pin, the corresponding bits in the LCDSEn registers must be set to `1'. If the pin is a digital I/O, the corresponding TRIS bit controls the data direction. Any bit set in the LCDSEn registers overrides any bit settings in the corresponding TRIS register. Note: On a Power-on Reset, these pins are configured as digital I/O.
9.5
Pixel Control
The LCDDATAx registers contain bits which define the state of each pixel. Each bit defines one unique pixel. Register 9-4 shows the correlation of each bit in the LCDDATAx registers to the respective common and segment signals. Any LCD pixel location not being used for display can be used as general purpose RAM.
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FIGURE 9-3:
FOSC
LCD CLOCK GENERATION
/8192 /4 /32 /2 DUP TRIP QUAD LP<3:0> (LCDPS<3:0>) LMUX<1:0> (LCDCON<1:0>) LMUX<1:0> (LCDCON<1:0>) 4-bit Prog Presc STAT /1, 2, 3, 4 Ring Counter COM0 COM1 COM2 COM3 /32 CS<1:0> (LCDCON<3:2>)
T1OSC 32 kHz Crystal Osc.
LFINTOSC Nom FRC = 31 kHz
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FIGURE 9-4:
LCD Function LCDDATAx Address LCDDATA3, 0 LCDDATA3, 1 LCDDATA3, 2 LCDDATA3, 3 LCDDATA3, 4 LCDDATA3, 5 LCDDATA3, 6 LCDDATA3, 7 LCDDATA4, 0 LCDDATA4, 1 LCDDATA4, 2 LCDDATA4, 3 LCDDATA4, 4 LCDDATA4, 5 LCDDATA4, 6 LCDDATA4, 7 LCDDATA5, 0 LCDDATA5, 1 LCDDATA5, 2 LCDDATA5, 3 LCDDATA5, 4 LCDDATA5, 5 LCDDATA5, 6 LCDDATA5, 7 LCDDATA8, 2 LCDDATA8, 3 LCDDATA8, 4 LCDDATA8, 5 LCDDATA8, 6 LCDDATA8, 7 LCDDATA8, 1 LCDDATA8, 0 LCDDATA7, 7 LCDDATA7, 6 LCDDATA7, 5 LCDDATA7, 4 LCDDATA7, 3 LCDDATA10, 3 LCDDATA10, 4 LCDDATA10, 5 LCDDATA10, 6 LCDDATA10, 7 LCDDATA11, 0 LCDDATA11, 1 LCDDATA11, 2 LCDDATA11, 3 LCDDATA11, 4 LCDDATA11, 5 LCDDATA11, 6 LCDDATA11, 7 LCDDATA7, 2 LCDDATA10, 2 LCDDATA7, 1 LCDDATA10, 1 LCDDATA7, 0 LCDDATA10, 0 LCDDATA6, 7 LCDDATA9, 7 LCDDATA6, 6 LCDDATA9, 6 LCDDATA6, 5 LCDDATA9, 5 7/7 14/18 3/3 18/26 17/25 16/24 15/23 2/2 28/40 27/39 5/5 -/26 -/27 -/28 -/29 -/30 -/8 -/9 -/10 LCDDATA6, 4 LCDDATA9, 4 6/6 LCDDATA6, 3 LCDDATA9, 3 24/36 LCDDATA6, 2 LCDDATA9, 2 23/35 RB2 RB3 RA4 RA5 RC3 RA1 RC7 RC6 RC5 RC4 RA0 RB7 RB6 RA3 RD3 RD4 RD5 RD6 RD7 RE0 RE1 RE2 AN5 AN6 AN7 AN1 LCDDATA6, 1 LCDDATA9, 1 22/34 RB1 LCDDATA6, 0 LCDDATA9, 0 21/33 RB0 LCD Segment LCDDATAx Address LCD Segment LCDDATAx Address LCD Segment 28/40-pin INT
COM0
COM1
COM2
COM3
Pin No.
PORT
Alternate Functions
LCDDATAx Address
LCD Segment
SEG0
LCDDATA0, 0
SEG1
LCDDATA0, 1
(c) 2005 Microchip Technology Inc.
C1OUT/T0CKI C2OUT/AN4/SS RX/DT/SDI/SDA TX/CK/SCK/SCL T1CKI/CCP1 T1G/SDO AN0 ICSPDAT/ICDDAT ICSPCK/ICDCK AN3/VREF+
SEG2
LCDDATA0, 2
SEG3
LCDDATA0, 3
SEG4
LCDDATA0, 4
SEG5
LCDDATA0, 5
SEG6
LCDDATA0, 6
SEG7
LCDDATA0, 7
SEG8
LCDDATA1, 0
SEG9
LCDDATA1, 1
SEG10
LCDDATA1, 2
SEG11
LCDDATA1, 3
LCD SEGMENT MAPPING WORKSHEET
Preliminary
SEG12
LCDDATA1, 4
SEG13
LCDDATA1, 5
SEG14
LCDDATA1, 6
SEG15
LCDDATA1, 7
SEG16
LCDDATA2, 0
SEG17
LCDDATA2, 1
SEG18
LCDDATA2, 2
SEG19
LCDDATA2, 3
SEG20
LCDDATA2, 4
SEG21
LCDDATA2, 5
SEG22
LCDDATA2, 6
SEG23
LCDDATA2, 7
PIC16F917/916/914/913
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9.7 LCD Waveform Generation
LCD waveforms are generated so that the net AC voltage across the dark pixel should be maximized and the net AC voltage across the clear pixel should be minimized. The net DC voltage across any pixel should be zero. The COM signal represents the time slice for each common, while the SEG contains the pixel data. The pixel signal (COM-SEG) will have no DC component and it can take only one of the two rms values. The higher rms value will create a dark pixel and a lower rms value will create a clear pixel. As the number of commons increases, the delta between the two rms values decreases. The delta represents the maximum contrast that the display can have. The LCDs can be driven by two types of waveform: Type-A and Type-B. In Type-A waveform, the phase changes within each common type, whereas in Type-B waveform, the phase changes on each frame boundary. Thus, Type-A waveform maintains 0 VDC over a single frame, whereas Type-B waveform takes two frames. Note 1: If Sleep has to be executed with LCD Sleep enabled (LCDCON is `1'), then care must be taken to execute Sleep only when VDC on all the pixels is `0'. 2: When the LCD clock source is FOSC/8192, if Sleep is executed, irrespective of the LCDCON setting, the LCD goes into Sleep. Thus, take care to see that VDC on all pixels is `0' when Sleep is executed. Figure 9-5 through Figure 9-15 provide waveforms for static, half-multiplex, one-third-multiplex and quarter-multiplex drives for Type-A and Type-B waveforms.
FIGURE 9-5:
TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE
V1 COM0 COM0 SEG0 V0 V1 V0 V1 V0 V1 COM0-SEG0 V0 -V1 COM0-SEG1 1 Frame SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 V0
SEG1
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FIGURE 9-6: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE
V2 COM0 COM1 COM1 V1 V0 V2 COM0 V1 V0 V2 SEG0 V1 V0 V2 SEG1 V1 V0 V2 V1 V0 -V1 -V2 V2 V1 COM0-SEG1 V0 -V1 -V2 1 Frame
SEG3
SEG2
SEG1 SEG0 COM0-SEG0
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FIGURE 9-7: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE
V2 COM1 COM0 V1 V0 COM0 COM1
V2 V1 V0
SEG0
V2 V1 V0
SEG2
SEG1 SEG0
SEG3
SEG1
V2 V1 V0
V2 V1 COM0-SEG0 V0 -V1 -V2
V2 V1 COM0-SEG1 V0 -V1 -V2 2 Frames
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FIGURE 9-8: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE
V3 COM0 COM1 V2 V1 V0 COM0 COM1 V3 V2 V1 V0 V3 SEG0 V2 V1 V0 V3 SEG3 SEG2 SEG1 SEG0 SEG1 V2 V1 V0
V3 V2 V1 COM0-SEG0 V0 -V1 -V2 -V3
V3 V2 V1 COM0-SEG1 V0 -V1 -V2 1 Frame -V3
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FIGURE 9-9: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE
V3 COM0 COM1 V2 V1 V0 COM0 COM1 V3 V2 V1 V0 V3 SEG0 V2 V1 V0 V3 SEG3 SEG2 SEG1 SEG0 SEG1 V2 V1 V0
V3 V2 V1 COM0-SEG0 V0 -V1 -V2 -V3
V3 V2 V1 COM0-SEG1 V0 -V1 -V2 2 Frames -V3
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FIGURE 9-10: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE
V2 COM0 V1 V0 V2 COM2 COM1 V1 V0 COM1 COM0 COM2 V2 V1 V0 V2 SEG0 SEG2 V1 V0 V2 SEG1 SEG2 SEG1 SEG0 V1 V0 V2 V1 COM0-SEG0 V0 -V1 -V2 V2 V1 COM0-SEG1 V0 -V1 -V2 1 Frame
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FIGURE 9-11: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE
COM0
V2 V1 V0
COM2 COM1 COM1 COM0 V2 V1 V0
COM2
V2 V1 V0
SEG0 SEG2 SEG1 SEG0
V2 V1 V0 V2 V1 V0 V2 V1
SEG1
COM0-SEG0
V0 -V1 -V2
V2 V1 COM0-SEG1 V0 -V1 -V2 2 Frames
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FIGURE 9-12: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE
V3 COM0 V2 V1 V0 COM2 COM1 COM1 COM0 V3 V2 V1 V0 V3 COM2 V2 V1 V0 V3 V2 SEG0 SEG2 SEG2 SEG1 SEG0 V1 V0 V3 SEG1 V2 V1 V0 V3 V2 V1 COM0-SEG0 V0 -V1 -V2 -V3 V3 V2 V1 COM0-SEG1 V0 -V1 -V2 -V3 1 Frame
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FIGURE 9-13: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE
V3 COM0 V2 V1 V0 COM2 COM1 COM1 COM0 V3 V2 V1 V0 V3 COM2 V2 V1 V0 V3 SEG0 SEG2 SEG1 SEG0 V2 V1 V0 V3 SEG1 V2 V1 V0 V3 V2 V1 COM0-SEG0 V0 -V1 -V2 -V3 V3 V2 V1 COM0-SEG1 V0 -V1 -V2 -V3 2 Frames
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FIGURE 9-14:
COM3 COM2 COM0
V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 -V1 -V2 -V3 V3 V2 V1 V0 -V1 -V2 -V3
TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE
COM1 COM0
COM1
COM2
COM3
SEG0 SEG1 SEG0
SEG1
COM0-SEG0
COM0-SEG1
1 Frame
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FIGURE 9-15:
COM3 COM2 COM0
V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 -V1 -V2 -V3 V3 V2 V1 V0 -V1 -V2 -V3
TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE
COM1 COM0
COM1
COM2
COM3
SEG0 SEG1 SEG0
SEG1
COM0-SEG0
COM0-SEG1
2 Frames
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9.8 LCD Interrupts
The LCD timing generation provides an interrupt that defines the LCD frame timing. This interrupt can be used to coordinate the writing of the pixel data with the start of a new frame. Writing pixel data at the frame boundary allows a visually crisp transition of the image. This interrupt can also be used to synchronize external events to the LCD. A new frame is defined to begin at the leading edge of the COM0 common signal. The interrupt will be set immediately after the LCD controller completes accessing all pixel data required for a frame. This will occur at a fixed interval before the frame boundary (TFINT), as shown in Figure 9-16. The LCD controller will begin to access data for the next frame within the interval from the interrupt to when the controller begins to access data after the interrupt (TFWR). New data must be written within TFWR, as this is when the LCD controller will begin to access the data for the next frame. When the LCD driver is running with Type-B waveforms and the LMUX<1:0> bits are not equal to `00', there are some additional issues that must be addressed. Since the DC voltage on the pixel takes two frames to maintain zero volts, the pixel data must not change between subsequent frames. If the pixel data were allowed to change, the waveform for the odd frames would not necessarily be the complement of the waveform generated in the even frames and a DC component would be introduced into the panel. Therefore, when using Type-B waveforms, the user must synchronize the LCD pixel updates to occur within a subframe after the frame interrupt. To correctly sequence writing while in Type-B, the interrupt will only occur on complete phase intervals. If the user attempts to write when the write is disabled, the WERR (LCDCON<5>) bit is set. Note: The interrupt is not generated when the Type-A waveform is selected and when the Type-B with no multiplex (static) is selected.
FIGURE 9-16:
WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY CYCLE DRIVE (EXAMPLE - TYPE-B, NON-STATIC)
LCD Interrupt Occurs Controller Accesses Next Frame Data V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0
COM0
COM1
COM2
COM3
2 Frames TFINT Frame Boundary TFWR = TFRAME/2*(LMUX<1:0> + 1) + TCY/2 TFINT = (TFWR/2 - (2 TCY + 40 ns)) minimum = 1.5(TFRAME/4) - (2 TCY + 40 ns) (TFWR/2 - (1 TCY + 40 ns)) maximum = 1.5(TFRAME/4) - (1 TCY + 40 ns) Frame Boundary TFWR Frame Boundary
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9.9 Operation During Sleep
The LCD module can operate during Sleep. The selection is controlled by bit SLPEN (LCDCON<6>). Setting the SLPEN bit allows the LCD module to go to Sleep. Clearing the SLPEN bit allows the module to continue to operate during Sleep. If a SLEEP instruction is executed and SLPEN = 1, the LCD module will cease all functions and go into a very low-current Consumption mode. The module will stop operation immediately and drive the minimum LCD voltage on both segment and common lines. Figure 9-17 shows this operation. To ensure that no DC component is introduced on the panel, the SLEEP instruction should be executed immediately after a LCD frame boundary. The LCD interrupt can be used to determine the frame boundary. See Section 9.8 "LCD Interrupts" for the formulas to calculate the delay. If a SLEEP instruction is executed and SLPEN = 0, the module will continue to display the current contents of the LCDDATA registers. To allow the module to continue operation while in Sleep, the clock source must be either the LFINTOSC or T1OSC external oscillator. While in Sleep, the LCD data cannot be changed. The LCD module current consumption will not decrease in this mode; however, the overall consumption of the device will be lower due to shut down of the core and other peripheral functions. Table 9-4 shows the status of the LCD module during a Sleep while using each of the three available clock sources:
TABLE 9-4:
LCD MODULE STATUS DURING SLEEP
SLPEN 0 1 0 1 0 1 Operation During Sleep? Yes No Yes No No No
Clock Source T1OSC LFINTOSC FOSC/4
Note:
The LFINTOSC or external T1OSC oscillator must be used to operate the LCD module during Sleep.
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FIGURE 9-17: SLEEP ENTRY/EXIT WHEN SLPEN = 1 OR CS<1:0> = 00
V3 V2 V1 COM0 V0 V3 V2 V1 COM1 V0 V3 V2 V1 COM2 V0 V3 V2 V1 SEG0 V0 2 Frames SLEEP Instruction Execution Wake-up
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9.10 Configuring the LCD Module
4. 5. The following is the sequence of steps to configure the LCD module. 1. 2. 3. Select the frame clock prescale using bits LP<3:0> (LCDPS<3:0>). Configure the appropriate pins to function as segment drivers using the LCDSEn registers. Configure the LCD module for the following using the LCDCON register: -Multiplex and Bias mode, bits LMUX<1:0> -Timing source, bits CS<1:0> -Sleep mode, bit SLPEN Write initial values to pixel data registers, LCDDATA0 through LCDDATA11. Clear LCD Interrupt Flag, LCDIF (PIR2<4>) and if desired, enable the interrupt by setting bit LCDIE (PIE2<4>). Enable bias voltage pins (VLCD<3:1>) by setting VLCDEN (LCDCON<4>). Enable the LCD module by setting bit LCDEN (LCDCON<7>).
6. 7.
TABLE 9-5:
Address
REGISTERS ASSOCIATED WITH LCD OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets uuuu uuuu 0000 000x 0000 -0-0 0000 -0-0 0001 0011 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
10h 0Bh/8Bh/ 10Bh/18Bh 0Dh 8Dh 107h 108h 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh Legend: Note 1: 2: 3:
T1CON INTCON PIR2 PIE2 LCDCON LCDPS LCDDATA0 LCDDATA1 LCDDATA2(2) LCDDATA3 LCDDATA4 LCDDATA5(2) LCDDATA6 LCDDATA7 LCDDATA8(2) LCDDATA9 LCDDATA10 LCDDATA11(2) LCDSE0(3) LCDSE1
(3)
T1GINV GIE OSFIF OSFIE LCDEN WFT SEG7 COM0 SEG15 COM0 SEG23 COM0 SEG7 COM1 SEG15 COM1 SEG23 COM1 SEG7 COM2 SEG15 COM2 SEG23 COM2 SEG7 COM3 SEG15 COM3 SEG23 COM3 SE7 SE15 SE23
T1GE PEIE C2IF C2IE SLPEN BIASMD SEG6 COM0 SEG14 COM0 SEG22 COM0 SEG6 COM1 SEG14 COM1 SEG22 COM1 SEG6 COM2 SEG14 COM2 SEG22 COM2 SEG6 COM3 SEG14 COM3 SEG22 COM3 SE6 SE14 SE22
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 T0IE C1IF C1IE WERR LCDA SEG5 COM0 SEG13 COM0 SEG21 COM0 SEG5 COM1 SEG13 COM1 SEG21 COM1 SEG5 COM2 SEG13 COM2 SEG21 COM2 SEG5 COM3 SEG13 COM3 SEG21 COM3 SE5 SE13 SE21 INTE LCDIF LCDIE VLCDEN WA SEG4 COM0 SEG12 COM0 SEG20 COM0 SEG4 COM1 SEG12 COM1 SEG20 COM1 SEG4 COM2 SEG12 COM2 SEG20 COM2 SEG4 COM3 SEG12 COM3 SEG20 COM3 SE4 SE12 SE20 RBIE -- -- CS1 LP3 SEG3 COM0 SEG11 COM0 SEG19 COM0 SEG3 COM1 SEG11 COM1 SEG19 COM1 SEG3 COM2 SEG11 COM2 SEG19 COM2 SEG3 COM3 SEG11 COM3 SEG19 COM3 SE3 SE11 SE19 T0IF LVDIF LVDIE CS0 LP2 SEG2 COM0 SEG10 COM0 SEG18 COM0 SEG2 COM1 SEG10 COM1 SEG18 COM1 SEG2 COM2 SEG10 COM2 SEG18 COM2 SEG2 COM3 SEG10 COM3 SEG18 COM3 SE2 SE10 SE18 INTF -- -- LMUX1 LP1 SEG1 COM0 SEG9 COM0 SEG17 COM0 SEG1 COM1 SEG9 COM1 SEG17 COM1 SEG1 COM2 SEG9 COM2 SEG17 COM2 SEG1 COM3 SEG9 COM3 SEG17 COM3 SE1 SE9 SE17 RBIF CCP2IF CCP2IE LMUX0 LP0 SEG0 COM0 SEG8 COM0 SEG16 COM0 SEG0 COM1 SEG8 COM1 SEG16 COM1 SEG0 COM2 SEG8 COM2 SEG16 COM2 SEG0 COM3 SEG8 COM3 SEG16 COM3 SE0 SE8 SE16 0000 000x 0000 -0-0 0000 -0-0 0001 0011 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000
LCDSE2(2,3)
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the LCD module. These pins may be configured as port pins, depending on the oscillator mode selected. PIC16F914/917 only. This register is only initialized by a POR or BOR reset and is unchanged by other Resets.
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10.0 PROGRAMMABLE LOW-VOLTAGE DETECT (PLVD) MODULE
10.1.1 PLVD CALIBRATION
The PIC16F91X stores the PLVD calibration values in fuses located in the Calibration Word 2 (2009h). The Calibration Word 2 is not erased when using the specified bulk erase sequence in the "PIC16F91X Memory Programming Specification" (DS41244) and thus, does not require reprogramming.
The Programmable Low-Voltage Detect module is an interrupt driven supply level detection. The voltage detection monitors the internal power supply.
10.1
Voltage Trip Points
The PIC16F917/916/914/913 device supports eight internal PLVD trip points. See Register 10-1 for available PLVD trip point voltages.
REGISTER 10-1:
LVDCON - LOW-VOLTAGE DETECT CONTROL REGISTER (ADDRESS: 109h)
U-0 -- bit 7 U-0 -- R-0 IRVST R/W-0 LVDEN U-0 -- R/W-1 LVDL2 R/W-0 LVDL1 R/W-0 LVDL0 bit 0
bit 7-6 bit 5
Unimplemented: Read as `0' IRVST: Internal Reference Voltage Stable Status Flag bit(1) 1 = Indicates that the PLVD is stable and PLVD interrupt is reliable 0 = Indicates that the PLVD is not stable and PLVD interrupt should not be enabled LVDEN: Low-Voltage Detect Power Enable bit 1 = Enables PLVD, powers up PLVD circuit and supporting reference circuitry 0 = Disables PLVD, powers down PLVD and supporting circuitry Unimplemented: Read as `0' LVDL<2:0>: Low-Voltage Detection Limit bits (nominal values) 111 = 4.5V 110 = 4.2V 101 = 4.0V 100 = 2.3V (default) 011 = 2.2V 010 = 2.1V 001 = 2.0V 000 = 1.9V(2) Note 1: The IRVST bit is usable only when the HFINTOSC is running. When using an external crystal to run the microcontroller, the PLVD settling time is expected to be <50 s when VDD = 5V and <25 s when VDD = 3V. Appropriate software delays should be used after enabling the PLVD module to ensure proper status readings of the module. 2: Not tested and below minimum VDD. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 4
bit 3 bit 2-0
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TABLE 10-1:
Address
REGISTERS ASSOCIATED WITH PROGRAMMABLE LOW-VOLTAGE DETECT
Bit 7 GIE OSFIF OSFIE -- Bit 6 PEIE C2IF C2IE -- Bit 5 T0IE C1IF C1IE IRVST Bit 4 INTE LCDIF LCDIE LVDEN Bit 3 RBIE -- -- -- Bit 2 T0IF LVDIF LVDIE LVDL2 Bit 1 INTF -- -- LVDL1 Bit 0 RBIF Value on POR, BOR Value on all other Resets
Name
0Bh/8Bh/ INTCON 10Bh/18Bh 0Dh 8Dh 109h Legend: PIR2 PIE2 LVDCON
0000 000x 0000 000x
CCP2IF 0000 -0-0 0000 -0-0 CCP2IE 0000 -0-0 0000 -0-0 LVDL0 --00 -100 --00 -100
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the PLVD module.
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11.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART)
The USART can be configured in the following modes: * Asynchronous (full-duplex) * Synchronous - Master (half-duplex) * Synchronous - Slave (half-duplex) Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be set in order to configure pins RC6/TX/CK/SCK/SCL/SEG9 and RC7/RX/DT/SDI/SDA/SEG8 as the Universal Synchronous Asynchronous Receiver Transmitter. The USART module also has a multi-processor communication capability using 9-bit address detection.
The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The USART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers, or it can be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc.
REGISTER 11-1:
TXSTA - TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0 CSRC bit 7 R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC U-0 -- R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0
bit 7
CSRC: Clock Source Select bit Asynchronous mode: Don't care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in Sync mode.
bit 6
bit 5
bit 4
SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode Unimplemented: Read as `0' BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: 9th bit of Transmit Data, can be Parity bit Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 3 bit 2
bit 1
bit 0
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REGISTER 11-2: RCSTA - RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0 SPEN bit 7 bit 7 SPEN(1): Serial Port Enable bit 1 = Serial port enabled (configures RC7/RX/DT/SDI/SDA/SEG8 and RC6/TX/CK/SCK/SCL/SEG9 pins as serial port pins) 0 = Serial port disabled RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don't care Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete Synchronous mode - Slave: Don't care. CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and load of the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error RX9D: 9th bit of Received Data (can be parity bit but must be calculated by user firmware) Note 1: CCP2CON used for PIC16F914/917 only. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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11.1 USART Baud Rate Generator (BRG)
It may be advantageous to use the high baud rate (BRGH = 1) even for slower baud clocks. This is because the FOSC/(16 (X + 1)) equation can reduce the baud rate error in some cases. Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate.
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate. In Synchronous mode, bit BRGH is ignored. Table 11-1 shows the formula for computation of the baud rate for different USART modes which only apply in Master mode (internal clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRG register can be calculated using the formula in Table 11-1. From this, the error in baud rate can be determined.
11.1.1
SAMPLING
The data on the RC7/RX/DT/SDI/SDA/SEG8 pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin.
TABLE 11-1:
SYNC 0 1
BAUD RATE FORMULA
BRGH = 0 (Low Speed) (Asynchronous) Baud Rate = FOSC/(64 (X + 1)) (Synchronous) Baud Rate = FOSC/(4 (X + 1)) BRGH = 1 (High Speed) Baud Rate = FOSC/(16 (X + 1)) N/A
Legend: X = value in SPBRG (0 to 255)
TABLE 11-2:
Address 98h 18h 99h
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Bit 7 CSRC SPEN
-
Name TXSTA RCSTA
Bit 6 TX9 RX9
Bit 5 TXEN
Bit 4 SYNC
Bit 3 --
Bit 2 BRGH FERR
Bit 1 TRMT
Bit 0
Value on: POR, BOR
Value on all other Resets
TX9D 0000 -010 0000 -010 0000 0000 0000 0000
SREN CREN ADDEN
OERR RX9D 0000 000x 0000 000x
SPBRG Baud Rate Generator Register
Legend: x = unknown,
= unimplemented, read as `0'. Shaded cells are not used by the BRG.
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TABLE 11-3:
BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 28.8 33.6 57.6 HIGH LOW BAUD RATE (K) KBAUD 0.3 1.2 2.4 9.6 19.2 28.8 33.6 57.6 HIGH LOW 0.300 1.202 2.404 8.929 20.833 31.250 -- 62.500 0.244 62.500
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 20 MHz % ERROR -- 1.75 0.17 1.73 1.72 8.51 3.34 8.51 -- -- FOSC = 4 MHz % ERROR 0 0.17 0.17 6.99 8.51 8.51 -- 8.51 -- -- SPBRG value (decimal) 207 51 25 6 2 1 -- 0 255 0 SPBRG value (decimal) -- 255 129 31 15 9 8 4 255 0 FOSC = 16 MHz % ERROR -- 0.17 0.17 0.16 0.16 3.55 6.29 8.51 -- -- SPBRG value (decimal) -- 207 103 25 12 8 6 3 255 0 FOSC = 10 MHz % ERROR -- 0.17 0.17 1.73 1.72 8.51 6.99 9.58 -- -- SPBRG value (decimal) -- 129 64 15 7 4 4 2 255 0
KBAUD -- 1.221 2.404 9.766 19.531 31.250 34.722 62.500 1.221 312.500
KBAUD -- 1.202 2.404 9.615 19.231 27.778 35.714 62.500 0.977 250.000
KBAUD -- 1.202 2.404 9.766 19.531 31.250 31.250 52.083 0.610 156.250
FOSC = 3.6864 MHz % ERROR 0 0 0 0 0 0 -- 0 -- -- SPBRG value (decimal) 191 47 23 5 2 1 -- 0 255 0
KBAUD 0.3 1.2 2.4 9.6 19.2 28.8 -- 57.6 0.225 57.6
TABLE 11-4:
BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 28.8 33.6 57.6 HIGH LOW BAUD RATE (K) KBAUD 0.3 1.2 2.4 9.6 19.2 28.8 33.6 57.6 HIGH LOW -- 1.202 2.404 9.615 19.231 27.798 35.714 62.500 0.977 250.000
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 20 MHz % ERROR -- -- -- 0.16 0.16 0.94 0.55 3.34 -- -- FOSC = 4 MHz % ERROR -- 0.17 0.17 0.16 0.16 3.55 6.29 8.51 -- -- SPBRG value (decimal) -- 207 103 25 12 8 6 3 255 0 SPBRG value (decimal) -- -- -- 129 64 42 36 20 255 0 FOSC = 16 MHz % ERROR -- -- -- 0.16 0.16 2.13 0.79 2.13 -- -- SPBRG value (decimal) -- -- -- 103 51 33 29 16 255 0 FOSC = 10 MHz % ERROR -- -- 1.71 0.16 1.72 1.36 2.10 1.36 SPBRG value (decimal) -- -- 255 64 31 21 18 10 255 0
KBAUD -- -- -- 9.615 19.231 29.070 33.784 59.524 4.883 1250.000
KBAUD -- -- -- 9.615 19.231 29.412 33.333 58.824 3.906 1000.000
KBAUD -- -- 2.441 9.615 19.531 28.409 32.895 56.818 2.441 625.000
FOSC = 3.6864 MHz % ERROR -- 0 0 0 0 0 2.04 0 -- -- SPBRG value (decimal) -- 191 95 23 11 7 6 3 255 0
KBAUD -- 1.2 2.4 9.6 19.2 28.8 32.9 57.6 0.9 230.4
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11.2 USART Asynchronous Mode
In this mode, the USART uses standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip, dedicated, 8-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and receives the LSb first. The transmitter and receiver are functionally independent but use the same data format and baud rate. The baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on bit BRGH (TXSTA<2>). Parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). Asynchronous mode is stopped during Sleep. Asynchronous mode is selected by clearing bit SYNC (TXSTA<4>). The USART Asynchronous module consists of the following important elements: * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver Transmission is enabled by setting enable bit, TXEN (TXSTA<5>). The actual transmission will not occur until the TXREG register has been loaded with data and the Baud Rate Generator (BRG) has produced a shift clock (Figure 11-2). The transmission can also be started by first loading the TXREG register and then setting enable bit TXEN. Normally, when transmission is first started, the TSR register is empty. At that point, transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. A back-to-back transfer is thus possible (Figure 11-3). Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter. As a result, the RC6/TX/CK/SCK/SCL/SEG9 pin will revert to high-impedance. In order to select 9-bit transmission, transmit bit TX9 (TXSTA<6>) should be set and the ninth bit should be written to TX9D (TXSTA<0>). The ninth bit must be written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG register can result in an immediate transfer of the data to the TSR register (if the TSR is empty). In such a case, an incorrect ninth data bit may be loaded in the TSR register. When setting up an Asynchronous Transmission, follow these steps: 1. Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH (Section 11.1 "USART Baud Rate Generator (BRG)"). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set transmit bit TX9. Enable the transmission by setting bit TXEN, which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set.
11.2.1
USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in Figure 11-1. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The shift register obtains its data from the Read/Write Transmit Buffer, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and flag bit, TXIF (PIR1<4>), is set. This interrupt can be enabled/disabled by setting/clearing enable bit, TXIE (PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. Status bit TRMT is a read-only bit which is set when the TSR register is empty. No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory, so it is not available to the user. 2: Flag bit TXIF is set when enable bit TXEN is set. TXIF is cleared by loading TXREG.
2. 3. 4. 5. 6. 7. 8.
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FIGURE 11-1: USART TRANSMIT BLOCK DIAGRAM
Data Bus TXIF TXIE MSb (8) Interrupt TXEN Baud Rate CLK TRMT SPBRG Baud Rate Generator TX9 TX9D SPEN TXREG Register 8 *** TSR Register LSb 0 Pin Buffer and Control RC6/TX/CK/SCK/ SCL/SEG9 pin
FIGURE 11-2:
Write to TXREG BRG Output (Shift Clock) RC6/TX/CK/ SCK/SCL/SEG9 TXIF bit (Transmit Buffer Reg. Empty Flag)
ASYNCHRONOUS MASTER TRANSMISSION
Word 1
Start bit
bit 0
bit 1 Word 1
bit 7/8
Stop bit
TRMT bit (Transmit Shift Reg. Empty Flag)
Word 1 Transmit Shift Reg
FIGURE 11-3:
Write to TXREG BRG Output (Shift Clock) RC6/TX/CK/ SCK/SCL/SEG9 TXIF bit (Interrupt Reg. Flag) TRMT bit (Transmit Shift Reg. Empty Flag) Note:
ASYNCHRONOUS MASTER TRANSMISSION (BACK-TO-BACK)
Word 1 Word 2
Start bit
bit 0
bit 1 Word 1
bit 7/8
Stop bit
Start bit Word 2
bit 0
Word 1 Transmit Shift Reg.
Word 2 Transmit Shift Reg.
This timing diagram shows two consecutive transmissions.
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TABLE 11-5:
Address
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7 GIE EEIF SPEN EEIE CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 T0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF ADDEN SSPIE -- Bit 2 T0IF CCP1IF FERR CCP1IE BRGH Bit 1 INTF TMR2IF OERR TMR2IE TRMT Bit 0 RBIF TMR1IF RX9D TMR1IE TX9D Value on: POR, BOR 0000 000x 0000 0000 0000 000x 0000 0000 0000 0000 0000 -010 0000 0000 Value on all other Resets 0000 000x 0000 0000 0000 000x 0000 0000 0000 0000 0000 -010 0000 0000
Name
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 19h 8Ch 98h 99h Legend: PIR1 RCSTA TXREG PIE1 TXSTA
USART Transmit Data Register
SPBRG Baud Rate Generator Register
x = unknown, - = unimplemented locations read as `0'. Shaded cells are not used for asynchronous transmission.
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PIC16F917/916/914/913
11.2.2 USART ASYNCHRONOUS RECEIVER
When setting up an Asynchronous Reception, follow these steps: Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH (Section 11.1 "USART Baud Rate Generator (BRG)"). 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 3. If interrupts are desired, then set enable bit RCIE. 4. If 9-bit reception is desired, then set bit RX9. 5. Enable the reception by setting bit CREN. 6. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE is set. 7. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. 1. The receiver block diagram is shown in Figure 11-4. The data is received on the RC7/RX/DT/SDI/SDA/SEG8 pin and drives the data recovery block. The data recovery block is actually a high-speed shifter, operating at x16 times the baud rate; whereas the main receive serial shifter operates at the bit rate or at FOSC. Once Asynchronous mode is selected, reception is enabled by setting bit CREN (RCSTA<4>). The heart of the receiver is the Receive (Serial) Shift Register (RSR). After sampling the Stop bit, the received data in the RSR is transferred to the RCREG register (if it is empty). If the transfer is complete, flag bit, RCIF (PIR1<5>), is set. The actual interrupt can be enabled/disabled by setting/clearing enable bit, RCIE (PIE1<5>). Flag bit RCIF is a read-only bit which is cleared by the hardware. It is cleared when the RCREG register has been read and is empty. The RCREG is a double-buffered register (i.e., it is a two-deep FIFO). It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the detection of the Stop bit of the third byte, if the RCREG register is still full, the Overrun Error bit, OERR (RCSTA<1>), will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Overrun bit OERR has to be cleared in software. This is done by resetting the receive logic (CREN is cleared and then set). If bit OERR is set, transfers from the RSR register to the RCREG register are inhibited and no further data will be received. It is, therefore, essential to clear error bit OERR if it is set. Framing error bit, FERR (RCSTA<2>), is set if a Stop bit is detected as clear. Bit FERR and the 9th receive bit are buffered the same way as the receive data. Reading the RCREG will load bits RX9D and FERR with new values, therefore, it is essential for the user to read the RCSTA register before reading the RCREG register in order not to lose the old FERR and RX9D information.
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Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
FIGURE 11-4: USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK CREN FOSC SPBRG Baud Rate Generator RC7/RX/DT/ SDI/SDA/SEG8 Pin Buffer and Control Data Recovery RX9 /64 or /16 MSb Stop (8) 7 RSR Register *** 1 0 LSb Start OERR FERR
SPEN
RX9D
RCREG Register
FIFO
8 Interrupt RCIF RCIE Data Bus
FIGURE 11-5:
RX (pin) Rcv Shift Reg Rcv Buffer Reg Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note:
ASYNCHRONOUS RECEPTION
Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit
Word 1 RCREG
Word 2 RCREG
This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word, causing the OERR (Overrun Error) bit to be set.
TABLE 11-6:
Address
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7 GIE EEIF SPEN EEIE CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 T0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF ADDEN SSPIE -- Bit 2 T0IF Bit 1 INTF Bit 0 RBIF Value on: POR, BOR 0000 000x 0000 0000 0000 000x 0000 0000 CCP1IE TMR2IE TMR1IE BRGH TRMT TX9D 0000 0000 0000 -010 0000 0000 Value on all other Resets 0000 000x 0000 0000 0000 000x 0000 0000 0000 0000 0000 -010 0000 0000
Name
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h Legend: PIR1 RCSTA PIE1 TXSTA SPBRG
CCP1IF TMR2IF TMR1IF FERR OERR RX9D
RCREG USART Receive Data Register
Baud Rate Generator Register
x = unknown, - = unimplemented locations read as `0'. Shaded cells are not used for asynchronous reception.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 135
PIC16F917/916/914/913
11.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT
When setting up an Asynchronous Reception with address detect enabled: * Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH. * Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. * If interrupts are desired, then set enable bit RCIE. * Set bit RX9 to enable 9-bit reception. * Set ADDEN to enable address detect. * Enable the reception by setting enable bit CREN. * Flag bit RCIF will be set when reception is complete, and an interrupt will be generated if enable bit RCIE was set. * Read the RCSTA register to get the ninth bit and determine if any error occurred during reception. * Read the 8-bit received data by reading the RCREG register to determine if the device is being addressed. * If any error occurred, clear the error by clearing enable bit CREN. * If the device has been addressed, clear the ADDEN bit to allow data bytes and address bytes to be read into the receive buffer and interrupt the CPU.
FIGURE 11-6:
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK CREN OERR FERR
FOSC
SPBRG / 64 or / 16 MSb Stop (8) 7 RSR Register *** 1 0 LSb Start
Baud Rate Generator RC7/RX/DT SDI/SDA/SEG8 Pin Buffer and Control
Data Recovery
RX9
8 SPEN
RX9 ADDEN RX9 ADDEN RSR<8>
Enable Load of Receive Buffer 8
RX9D
RCREG Register FIFO
8 Interrupt RCIF RCIE Data Bus
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Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
FIGURE 11-7:
RC7/RX/DT/ SDI/SDA/SEG8 Load RSR bit 8 = 0, Data Byte Read bit 8 = 1, Address Byte Word 1 RCREG
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
Start bit bit 0 bit 1 bit 8 Stop bit Start bit bit 0 bit 8 Stop bit
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer) because ADDEN = 1.
FIGURE 11-8:
RC7/RX/DT/ SDI/SDA/SEG8 Load RSR
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
Start bit bit 0 bit 1 bit 8 Stop bit Start bit bit 0 bit 8 Stop bit
bit 8 = 1, Address Byte Read
bit 8 = 0, Data Byte
Word 1 RCREG
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer) because ADDEN was not updated and still = 0.
TABLE 11-7:
Address
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7 GIE EEIF SPEN EEIE CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 T0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF Bit 3 RBIE SSPIF Bit 2 T0IF Bit 1 INTF Bit 0 RBIF Value on: POR, BOR Value on all other Resets
Name
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h Legend: PIR1 RCSTA RCREG PIE1 TXSTA SPBRG
0000 000x 0000 000x
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 FERR OERR RX9D 0000 000x 0000 000x 0000 0000 0000 0000
CREN ADDEN TXIE SYNC SSPIE --
USART Receive Data Register BRGH TRMT TX9D
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0000 -010 0000 -010 0000 0000 0000 0000
Baud Rate Generator Register
x = unknown, - = unimplemented locations read as `0'. Shaded cells are not used for asynchronous reception.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 137
PIC16F917/916/914/913
11.3 USART Synchronous Master Mode
Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter. The DT and CK pins will revert to high-impedance. If either bit CREN or bit SREN is set during a transmission, the transmission is aborted and the DT pin reverts to a high-impedance state (for a reception). The CK pin will remain an output if bit CSRC is set (internal clock). The transmitter logic, however, is not reset, although it is disconnected from the pins. In order to reset the transmitter, the user has to clear bit TXEN. If bit SREN is set (to interrupt an on-going transmission and receive a single word), then after the single word is received, bit SREN will be cleared and the serial port will revert back to transmitting, since bit TXEN is still set. The DT line will immediately switch from High-Impedance Receive mode to transmit and start driving. To avoid this, bit TXEN should be cleared. In order to select 9-bit transmission, the TX9 (TXSTA<6>) bit should be set and the ninth bit should be written to bit TX9D (TXSTA<0>). The ninth bit must be written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG can result in an immediate transfer of the data to the TSR register (if the TSR is empty). If the TSR was empty and the TXREG was written before writing the "new" TX9D, the "present" value of bit TX9D is loaded. Steps to follow when setting up a Synchronous Master Transmission: 1. Initialize the SPBRG register for the appropriate baud rate (Section 11.1 "USART Baud Rate Generator (BRG)"). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set.
In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit, SYNC (TXSTA<4>). In addition, enable bit, SPEN (RCSTA<7>), is set in order to configure the RC6/TX/CK/SCK/SCL/SEG9 and RC7/RX/DT/SDI/SDA/SEG8 I/O pins to CK (clock) and DT (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on the CK line. The Master mode is entered by setting bit, CSRC (TXSTA<7>).
11.3.1
USART SYNCHRONOUS MASTER TRANSMISSION
The USART transmitter block diagram is shown in Figure 11-6. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The shift register obtains its data from the Read/Write Transmit Buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG is empty and interrupt bit, TXIF (PIR1<4>), is set. The interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. TRMT is a read-only bit which is set when the TSR is empty. No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory so it is not available to the user. Transmission is enabled by setting enable bit, TXEN (TXSTA<5>). The actual transmission will not occur until the TXREG register has been loaded with data. The first data bit will be shifted out on the next available rising edge of the clock on the CK line. Data out is stable around the falling edge of the synchronous clock (Figure 11-9). The transmission can also be started by first loading the TXREG register and then setting bit TXEN (Figure 11-10). This is advantageous when slow baud rates are selected, since the BRG is kept in Reset when bits TXEN, CREN and SREN are clear. Setting enable bit TXEN will start the BRG, creating a shift clock immediately. Normally, when transmission is first started, the TSR register is empty, so a transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. Back-to-back transfers are possible.
2. 3. 4. 5. 6. 7. 8.
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Preliminary
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TABLE 11-8:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 7 GIE EEIF SPEN EEIE CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 T0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF Bit 3 RBIE SSPIF Bit 2 T0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR Bit 0 RBIF TMR1IF RX9D Value on: POR, BOR 0000 000x 0000 0000 0000 000x 0000 0000 SSPIE -- CCP1IE TMR2IE TMR1IE 0000 0000 BRGH TRMT TX9D 0000 -010 0000 0000 Value on all other Resets 0000 000x 0000 0000 0000 000x 0000 0000 0000 0000 0000 -010 0000 0000
Name
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 19h 8Ch 98h 99h Legend: PIR1 RCSTA PIE1 TXSTA
CREN ADDEN TXIE SYNC
TXREG USART Transmit Data Register
SPBRG Baud Rate Generator Register
x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous master transmission.
FIGURE 11-9:
SYNCHRONOUS TRANSMISSION
Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 bit 7 bit 0 bit 1 Word 2 bit 7
Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT/ SDI/SDA/SEG8 RC6/TX/CK/ SCK/SCL/SEG9 Write to TXREG reg Write Word 1 TXIF bit (Interrupt Flag) TRMT bit `1' Write Word 2 bit 0 bit 1 bit 2 Word 1
TXEN bit
`1'
Note: Sync Master mode; SPBRG = 0. Continuous transmission of two 8-bit words.
FIGURE 11-10:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
bit 0 bit 1 bit 2 bit 6 bit 7
RC7/RX/DT/SDI/SDA/SEG8 RC6/TX/CK/SCK/SCL/SEG9 Write to TXREG Reg
TXIF bit
TRMT bit
TXEN bit
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 139
PIC16F917/916/914/913
11.3.2 USART SYNCHRONOUS MASTER RECEPTION
When setting up a Synchronous Master Reception: 1. Initialize the SPBRG register for the appropriate baud rate (Section 11.1 "USART Baud Rate Generator (BRG)"). 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. Ensure bits CREN and SREN are clear. 4. If interrupts are desired, then set enable bit RCIE. 5. If 9-bit reception is desired, then set bit RX9. 6. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. Once Synchronous mode is selected, reception is enabled by setting either enable bit, SREN (RCSTA<5>), or enable bit, CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT/SDI/SDA/SEG8 pin on the falling edge of the clock. If enable bit SREN is set, then only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, CREN takes precedence. After clocking the last bit, the received data in the Receive Shift Register (RSR) is transferred to the RCREG register (if it is empty). When the transfer is complete, interrupt flag bit, RCIF (PIR1<5>), is set. The actual interrupt can be enabled/disabled by setting/clearing enable bit, RCIE (PIE1<5>). Flag bit RCIF is a read-only bit which is reset by the hardware. In this case, it is reset when the RCREG register has been read and is empty. The RCREG is a double-buffered register (i.e., it is a two-deep FIFO). It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting into the RSR register. On the clocking of the last bit of the third byte, if the RCREG register is still full, then Overrun Error bit, OERR (RCSTA<1>), is set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Bit OERR has to be cleared in software (by clearing bit CREN). If bit OERR is set, transfers from the RSR to the RCREG are inhibited so it is essential to clear bit OERR if it is set. The ninth receive bit is buffered the same way as the receive data. Reading the RCREG register will load bit RX9D with a new value, therefore, it is essential for the user to read the RCSTA register before reading RCREG in order not to lose the old RX9D information.
TABLE 11-9:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7 GIE EEIF SPEN EEIE CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 T0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF Bit 3 RBIE SSPIF Bit 2 T0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR Bit 0 RBIF TMR1IF RX9D Value on: POR, BOR 0000 000x 0000 0000 0000 000x 0000 0000 TXIE SYNC SSPIE -- CCP1IE TMR2IE TMR1IE 0000 0000 BRGH TRMT TX9D 0000 -010 0000 0000 Value on all other Resets 0000 000x 0000 0000 0000 000x 0000 0000 0000 0000 0000 -010 0000 0000
Name
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h Legend: PIR1 RCSTA RCREG PIE1 TXSTA SPBRG
CREN ADDEN
USART Receive Data Register
Baud Rate Generator Register
x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous master reception.
DS41250E-page 140
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
FIGURE 11-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 RC7/RX/DT/ SDI/SDA/SEG8 RC6/TX/CK/ SCK/SCL/SEG9 Write to bit SREN SREN bit CREN bit RCIF bit (Interrupt) Read RXREG `0' `0' bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
11.4
USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6/TX/CK/SCK/SCL/SEG9 pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in Sleep mode. Slave mode is entered by clearing bit, CSRC (TXSTA<7>).
When setting up a Synchronous Slave Transmission, follow these steps: 1. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set.
2. 3. 4. 5. 6. 7. 8.
11.4.1
USART SYNCHRONOUS SLAVE TRANSMIT
The operation of the Synchronous Master and Slave modes is identical, except in the case of the Sleep mode. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) b) c) d) The first word will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. Flag bit TXIF will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. If enable bit TXIE is set, the interrupt will wake the chip from Sleep and if the global interrupt is enabled, the program will branch to the interrupt vector (0004h).
e)
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 141
PIC16F917/916/914/913
TABLE 11-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Address Name Bit 7 GIE EEIF SPEN EEIE CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 T0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF ADDEN SSPIE -- Bit 2 T0IF Bit 1 INTF Bit 0 RBIF Value on: POR, BOR 0000 000x Value on all other Resets 0000 000x 0000 0000 0000 000x 0000 0000 0000 0000 0000 -010 0000 0000
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 19h 8Ch 98h 99h Legend: PIR1 RCSTA TXREG PIE1 TXSTA SPBRG
CCP1IF TMR2IF TMR1IF 0000 0000 FERR OERR RX9D 0000 000x 0000 0000 CCP1IE TMR2IE TMR1IE 0000 0000 BRGH TRMT TX9D 0000 -010 0000 0000
USART Transmit Data Register
Baud Rate Generator Register
x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous slave transmission.
11.4.2
USART SYNCHRONOUS SLAVE RECEPTION
When setting up a Synchronous Slave Reception, follow these steps: 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. To enable reception, set enable bit CREN. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit CREN. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set.
The operation of the Synchronous Master and Slave modes is identical, except in the case of the Sleep mode. Bit SREN is a "don't care" in Slave mode. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during Sleep. On completely receiving the word, the RSR register will transfer the data to the RCREG register and if enable bit RCIE bit is set, the interrupt generated will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector (0004h).
2. 3. 4. 5.
6.
7. 8. 9.
TABLE 11-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address Name Bit 7 GIE EEIF SPEN EEIE CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 T0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF ADDEN SSPIE -- Bit 2 T0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR Bit 0 RBIF Value on: POR, BOR Value on all other Resets
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h Legend: PIR1 RCSTA RCREG PIE1 TXSTA SPBRG
0000 000x 0000 000x
TMR1IF 0000 0000 0000 0000 RX9D 0000 000x 0000 000x 0000 0000 0000 0000
USART Receive Data Register BRGH TRMT TX9D
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0000 -010 0000 -010 0000 0000 0000 0000
Baud Rate Generator Register
x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous slave reception.
DS41250E-page 142
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
12.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
The Analog-to-Digital converter (A/D) allows conversion of an analog input signal to a 10-bit binary representation of that signal. The PIC16F917/916/914/913 has up to eight analog inputs, multiplexed into one sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a binary result via successive approximation and stores the result in a 10-bit register. The voltage reference used in the conversion is software selectable to either VDD or a voltage applied by the VREF pin. Figure 12-1 shows the block diagram of the A/D on the PIC16F917/916/914/913.
FIGURE 12-1:
A/D BLOCK DIAGRAM
VDD VCFG0 = 0 VREF+ VCFG0 = 1
RA0/AN0/C1-/SEG12 RA1/AN1/C2-/SEG7 RA2/AN2/C2+/VREF-/COM2 RA3/AN3/C1+/VREF+/COM3(2)/SEG15 RA5/AN4/C2OUT/SS/SEG5 RE0/AN5/SEG21(1) RE1/AN6/SEG22(1) RE2/AN7/SEG23(1) CHS<2:0> VREF-
A/D GO/DONE ADFM ADON VSS VCFG1 = 0 VCFG1 = 1 10 ADRESH ADRESL 10
Note 1: 2:
These channels are only available on PIC16F914/917 devices. COM3 available on RA3 only on PIC16F913/916 devices.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 143
PIC16F917/916/914/913
12.1 A/D Configuration and Operation
12.1.4 CONVERSION CLOCK
There are three registers available to control the functionality of the A/D module: 1. 2. 3. ANSEL (Register 12-1) ADCON0 (Register 12-2) ADCON1 (Register 12-3) The A/D conversion cycle requires 11 TAD. The source of the conversion clock is software selectable via the ADCS bits (ADCON1<6:4>). There are seven possible clock options: * * * * * * * FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal oscillator)
12.1.1
ANALOG PORT PINS
The ANS<7:0> bits (ANSEL<7:0>) and the TRIS bits control the operation of the A/D port pins. Set the corresponding TRIS bits to set the pin output driver to its high-impedance state. Likewise, set the corresponding ANSEL bit to disable the digital input buffer. Note: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current.
For correct conversion, the A/D conversion clock (1/TAD) must be selected to ensure a minimum TAD of 1.6 s. Table 12-1 shows a few TAD calculations for selected frequencies.
12.1.2
CHANNEL SELECTION
There are up to eight analog channels on the PIC16F917/916/914/913, AN<7:0>. The CHS<2:0> bits (ADCON0<4:2>) control which channel is connected to the sample and hold circuit.
12.1.3
VOLTAGE REFERENCE
There are two options for each reference to the A/D converter, VREF+ and VREF-. VREF+ can be connected to either VDD or an externally applied voltage. Alternatively, VREF- can be connected to either VSS or an externally applied voltage. VCFG<1:0> bits are used to select the reference source.
TABLE 12-1:
Operation 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC A/D RC Legend: Note 1: 2: 3: 4:
TAD vs. DEVICE OPERATING FREQUENCIES
Device Frequency 20 MHz 100 ns(2)
(2)
A/D Clock Source (TAD) ADCS<2:0> 000 100 001 101 010 110 x11 400
5 MHz ns(2) 800 ns(2) 1.6 s 3.2 s 6.4 s 12.8 s(3) 2-6 s(1,4)
4 MHz 500 ns(2) 1.0 s(2) 2.0 s 4.0 s 8.0 s(3) 16.0 s(3) 2-6 s(1,4)
1.25 MHz 1.6 s 3.2 s 6.4 s 12.8 s(3) 25.6 s(3) 51.2 s(3) 2-6 s(1,4)
200 ns(2) 400 ns 800 ns(2) 1.6 s 3.2 s 2-6 s(1,4)
Shaded cells are outside of recommended range. The A/D RC source has a typical TAD time of 4 s for VDD > 3.0V. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the conversion will be performed during Sleep.
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12.1.5 STARTING A CONVERSION
The A/D conversion is initiated by setting the GO/DONE bit (ADCON0<1>). When the conversion is complete, the A/D module: * Clears the GO/DONE bit * Sets the ADIF flag (PIR1<6>) * Generates an interrupt (if enabled) If the conversion must be aborted, the GO/DONE bit can be cleared in software. The ADRESH:ADRESL registers will not be updated with the partially complete A/D conversion sample. Instead, the ADRESH:ADRESL registers will retain the value of the previous conversion. After an aborted conversion, a 2 TAD delay is required before another acquisition can be initiated. Following the delay, an input acquisition is automatically started on the selected channel. Note: The GO/DONE bit should not be set in the same instruction that turns on the A/D.
FIGURE 12-2:
A/D CONVERSION TAD CYCLES
TCY TO TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion Starts Holding Capacitor is Disconnected from Analog Input (typically 100 ns) Set GO/DONE bit ADRESH and ADRESL registers are loaded, GO/DONE bit is cleared, ADIF bit is set, Holding Capacitor is Connected to Analog Input
12.1.6
CONVERSION OUTPUT
The A/D conversion can be supplied in two formats: left or right shifted. The ADFM bit (ADCON0<7>) controls the output format. Figure 12-3 shows the output formats.
FIGURE 12-3:
10-BIT A/D RESULT FORMAT
ADRESH ADRESL LSB bit 0 10-bit A/D Result bit 7 bit 0 Unimplemented: Read as `0' LSB bit 0 bit 7 bit 0
(ADFM = 0)
MSB bit 7
(ADFM = 1) bit 7 Unimplemented: Read as `0'
MSB
10-bit A/D Result
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REGISTER 12-1: ANSEL - ANALOG SELECT REGISTER (ADDRESS: 91h)
R/W-1 ANS7(2) bit 7 bit 7-0: ANS<7:0>: Analog Select bits(2) Select between analog or digital function on pins AN<7:0>, respectively. 1 = Analog input. Pin is assigned as analog input.(1) 0 = Digital I/O. Pin is assigned to port or special function. Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. 2: ANS<7:5> on PIC16F914/917 only; forced `0' on PIC16F913/916. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 ANS6(2) R/W-1 ANS5(2) R/W-1 ANS4 R/W-1 ANS3 R/W-1 ANS2 R/W-1 ANS1 R/W-1 ANS0 bit 0
REGISTER 12-2:
ADCON0 - A/D CONTROL REGISTER (ADDRESS: 1Fh)
R/W-0 ADFM bit 7 R/W-0 VCFG1 R/W-0 VCFG0 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 ADON bit 0
bit 7
ADFM: A/D Result Formed Select bit 1 = Right justified 0 = Left justified VCFG1: Voltage Reference bit 1 = VREF- pin 0 = VSS VCFG0: Voltage Reference bit 1 = VREF+ pin 0 = VDD CHS<2:0>: Analog Channel Select bits
000 = 001 = 010 = 011 = 100 = 101 = 110 = 111 = Channel 00 (AN0) Channel 01 (AN1) Channel 02 (AN2) Channel 03 (AN3) Channel 04 (AN4) Channel 05 (AN5) Channel 06 (AN6) Channel 07 (AN7)
bit 6
bit 5
bit 4-2
bit 1
GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress ADON: A/D Conversion Status bit 1 = A/D converter module is operating 0 = A/D converter is shut off and consumes no operating current Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 0
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REGISTER 12-3: ADCON1 - A/D CONTROL REGISTER 1 (ADDRESS: 9Fh)
U-0 -- bit 7 bit 7 bit 6-4 Unimplemented: Read as `0' ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 Unimplemented: Read as `0' Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 ADCS2 R/W-0 ADCS1 R/W-0 ADCS0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 3-0
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12.1.7 CONFIGURING THE A/D EXAMPLE 12-1: A/D CONVERSION
After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as inputs. To determine sample time, see Section 19.0 "Electrical Specifications". After this sample time has elapsed, the A/D conversion can be started. These steps should be followed for an A/D conversion: 1. Configure the A/D module: * Configure analog/digital I/O (ANSEL) * Configure voltage reference (ADCON0) * Select A/D input channel (ADCON0) * Select A/D conversion clock (ADCON1) * Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): * Clear ADIF bit (PIR1<6>) * Set ADIE bit (PIE1<6>) * Set PEIE and GIE bits (INTCON<7:6>) Wait the required acquisition time. Start conversion: * Set GO/DONE bit (ADCON0<1>) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared (with interrupts disabled); OR * Waiting for the A/D interrupt Read A/D Result register pair (ADRESH:ADRESL); clear bit ADIF if required. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts.
;This code block configures the A/D ;for polling, Vdd reference, R/C clock ;and RA0 input. ; ;Conversion start and wait for complete ;polling code included. ; BSF STATUS,RP0 ;Bank 1 MOVLW B'01110000' ;A/D RC clock MOVWF ADCON1 BSF TRISA,0 ;Set RA0 to input BSF ANSEL,0 ;Set RA0 to analog BCF STATUS,RP0 ;Bank 0 MOVLW B'10000001' ;Right, Vdd Vref, AN0 MOVWF ADCON0 CALL SampleTime ;Wait min sample time BSF ADCON0,GO ;Start conversion BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI BSF STATUS,RP0 ;Bank 1 MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO
2.
3. 4. 5.
6. 7.
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12.2 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 12-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 12-4. The maximum recommended impedance for analog sources is 10 k. As the impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 12-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. To calculate the minimum acquisition time, TACQ, see the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023).
EQUATION 12-1:
ACQUISITION TIME
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF = 2s + TC + [ ( Temperature - 25C ) ( 0.05s/C ) ] Where CHOLD is charged to within 1/2 lsb:
1VAPPLIED 1 - ----------- = VCHOLD 2047
--------- RC VAPPLIED 1 - e = VCHOLD -------- 1RC VAPPLIED 1 - e = VAPPLIED 1 - ----------- 2047 - Tc - TC
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD charge response to VAPPLIED
;combining [1] and [2]
Solving for TC:
TC = - CHOLD ( RIC + RSS + RS ) ln(1/2047) = - 10pF ( 1k + 7k + 10k ) ln(0.0004885) = 1.37 s
Therefore: TACQ = 2S + 1.37S + [ ( 50C- 25C ) ( 0.05S/C ) ] = 4.67S
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification.
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FIGURE 12-4: ANALOG INPUT MODEL
VDD RS VA ANx CPIN 5 pF VT = 0.6V RIC 1k I LEAKAGE 500 nA Sampling Switch SS RSS CHOLD = DAC capacitance = 10 pF VSS
VT = 0.6V
Legend: CPIN = Input Capacitance = Threshold Voltage VT I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance SS = Sampling Switch CHOLD = Sample/Hold Capacitance (from DAC)
6V 5V VDD 4V 3V 2V
RSS
5 6 7 8 9 10 11 Sampling Switch (k)
12.3
A/D Operation During Sleep
The A/D converter module can operate during Sleep. This requires the A/D clock source to be set to the internal oscillator. When the RC clock source is selected, the A/D waits one instruction before starting the conversion. This allows the SLEEP instruction to be executed, thus eliminating much of the switching noise from the conversion. When the conversion is complete, the GO/DONE bit is cleared and the result is loaded into the ADRESH:ADRESL registers. If the A/D
interrupt is enabled, the device awakens from Sleep. If the GIE bit (INTCON<7>) is set, the program counter is set to the interrupt vector (0004h). If GIE is clear, the next instruction is executed. If the A/D interrupt is not enabled, the A/D module is turned off, although the ADON bit remains set. When the A/D clock source is something other than RC, a SLEEP instruction causes the present conversion to be aborted, and the A/D module is turned off. The ADON bit remains set.
FIGURE 12-5:
A/D TRANSFER FUNCTION
Full-Scale Range 1 LSB Ideal 3FFh 3FEh 3FDh 3FCh 3FBh
1/2 LSB Ideal
A/D Output
004h 003h 002h 001h 000h 1/2 LSB Ideal
Full-Scale Transition
Center of Full-Scale Code
Analog Input VREF
Zero-Scale
Zero-Scale Transition
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12.4 Effects of Reset
A device Reset forces all registers to their Reset state. Thus, the A/D module is turned off and any pending conversion is aborted. The ADRESH:ADRESL registers are unchanged.
TABLE 12-2:
Addr 05h 09h 0Bh/ 8Bh 0Ch 1Eh 1Fh 85h 89h 8Ch 91h 9Eh 9Fh Name PORTA PORTE INTCON PIR1 ADRESH ADCON0 TRISA TRISE PIE1 ANSEL ADRESL ADCON1
SUMMARY OF A/D REGISTERS
Bit 7 RA7 -- GIE EEIF Bit 6 RA6 -- PEIE ADIF Bit 5 RA5 -- T0IE RCIF Bit 4 RA4 -- INTE TXIF Bit 3 RA3 RE3 RBIE SSPIF Bit 2 RA2 RE2 T0IF CCP1IF Bit 1 RA1 RE1 INTF TMR2IF Bit 0 RA0 RE0 RBIF TMR1IF Value on: POR, BOR xxxx xxxx ---- xxxx 0000 000x 0000 0000 xxxx xxxx ADON TRISA0 TRISE0 TMR1IE ANS0 0000 0000 1111 1111 ---- 1111 0000 0000 1111 1111 xxxx xxxx -- -000 ---Value on all other Resets uuuu uuuu ---- uuuu 0000 000x 0000 0000 uuuu uuuu 0000 0000 1111 1111 ---- 1111 0000 0000 1111 1111 uuuu uuuu -000 ----
Most Significant 8 bits of the left justified A/D result or 2 bits of the right justified result ADFM TRISA7 -- EEIE ANS7 VCFG1 TRISA6 -- ADIE ANS6 VCFG0 TRISA5 -- RCIE ANS5 CHS2 TRISA4 -- TXIE ANS4 CHS1 TRISA3 TRISE3 SSPIE ANS3 CHS0 TRISA2 TRISE2 CCP1IE ANS2 GO/DONE TRISA1 TRISE1 TMR2IE ANS1
Least Significant 2 bits of the left justified A/D result or 8 bits of the right justified result -- ADCS2 ADCS1 ADCS0 -- -- --
Legend:
x = unknown, u = unchanged, - = unimplemented read as `0'. Shaded cells are not used for A/D module.
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NOTES:
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13.0 DATA EEPROM AND FLASH PROGRAM MEMORY CONTROL
13.1 EEADRL and EEADRH Registers
The EEADRL and EEADRH registers can address up to a maximum of 256 bytes of data EEPROM or up to a maximum of 8k words of program EEPROM. When selecting a program address value, the MSB of the address is written to the EEADRH register and the LSB is written to the EEADRL register. When selecting a data address value, only the LSB of the address is written to the EEADRL register.
Data EEPROM memory is readable and writable and the Flash program memory is readable during normal operation (full VDD range). These memories are not directly mapped in the register file space. Instead, they are indirectly addressed through the Special Function Registers. There are six SFRs used to access these memories: * * * * * * EECON1 EECON2 EEDATL EEDATH EEADRL EEADRH
13.1.1
EECON1 AND EECON2 REGISTERS
EECON1 is the control register for EE memory accesses. Control bit EEPGD determines if the access will be a program or data memory access. When clear, as it is when reset, any subsequent operations will operate on the data memory. When set, any subsequent operations will operate on the program memory. Program memory can only be read. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation to data EEPROM. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR or a WDT Time-out Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit and rewrite the location. The data and address will be unchanged in the EEDATL and EEADRL registers. Interrupt flag bit EEIF (PIR1<7>), is set when write is complete. It must be cleared in the software. EECON2 is not a physical register. Reading EECON2 will read all `0's. The EECON2 register is used exclusively in the data EEPROM write sequence.
When interfacing the data memory block, EEDATL holds the 8-bit data for read/write, and EEADRL holds the address of the EE data location being accessed. This device has 256 bytes of data EEPROM with an address range from 0h to 0FFh. When interfacing the program memory block, the EEDATL and EEDATH registers form a 2-byte word that holds the 14-bit data for read, and the EEADRL and EEADRH registers form a 2-byte word that holds the 13-bit address of the EEPROM location being accessed. This device has 4k and 8k words of program EEPROM with an address range from 0h-0FFFh and 0h-1FFFh. The program memory allows one word reads. The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. When the device is code-protected, the CPU may continue to read and write the data EEPROM memory and read the program memory. When code-protected, the device programmer can no longer access data or program memory. Additional information on the data EEPROM is available in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023).
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REGISTER 13-1: EEDATL - EEPROM DATA LOW BYTE REGISTER (ADDRESS: 10Ch)
R/W-0 EEDATL7 bit 7 bit 7-0 R/W-0 EEDATL6 R/W-0 EEDATL5 R/W-0 EEDATL4 R/W-0 EEDATL3 R/W-0 EEDATL2 R/W-0 EEDATL1 R/W-0 EEDATL0 bit 0
EEDATL<7:0>: Byte value to Write to or Read from data EEPROM bits or to Read from program memory Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
REGISTER 13-2:
EEADRL - EEPROM ADDRESS LOW BYTE REGISTER (ADDRESS: 10Dh)
R/W-0 EEADRL7 bit 7 R/W-0 EEADRL6 R/W-0 EEADRL5 R/W-0 EEADRL4 R/W-0 EEADRL3 R/W-0 EEADRL2 R/W-0 EEADRL1 R/W-0 EEADRL0 bit 0
bit 7-0
EEADRL<7:0>: Specifies one of 256 locations for EEPROM Read/Write operation bits or low byte for program memory reads Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
REGISTER 13-3:
EEDATH - EEPROM DATA HIGH BYTE REGISTER (ADDRESS: 10Eh)
U-0 -- bit 7 U-0 -- R/W-0 EEDATH5 R/W-0 EEDATH4 R/W-0 EEDATH3 R/W-0 R/W-0 R/W-0 EEDATH0 bit 0 EEDATH2 EEDATH1
bit 5-0
EEDATH<5:0>: Byte value to Write to or Read from data EEPROM bits or to Read from program memory Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
REGISTER 13-4:
EEADRH - EEPROM ADDRESS HIGH BYTE REGISTER (ADDRESS: 10Fh)
U-0 -- bit 7 U-0 -- U-0 -- R/W-0 EEADRH4 R/W-0 EEADRH3 R/W-0 EEADRH2 R/W-0 EEADRH1 R/W-0 EEADRH0 bit 0
bit 4-0
EEADRH<4:0>: Specifies one of 256 locations for EEPROM Read/Write operation bits or high bits for program memory reads Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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REGISTER 13-5: EECON1 - EEPROM CONTROL REGISTER 1 (ADDRESS: 18Ch)
R/W-0 EEPGD bit 7 bit 7 EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses data memory Unimplemented: Read as `0' WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during normal operation or BOR Reset) 0 = The write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM WR: Write Control bit EEPGD = 1: This bit is ignored EEPGD = 0: 1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only be set, not cleared, in software.) 0 = Write cycle to the data EEPROM is complete RD: Read Control bit 1 = Initiates a memory read (RD is cleared in hardware. The RD bit can only be set, not cleared, in software.) 0 = Does not initiate an memory read Legend: S = Bit can only be set R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0
bit 6-4 bit 3
bit 2
bit 1
bit 0
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13.1.2 READING THE DATA EEPROM MEMORY
The steps to write to EEPROM data memory are: If step 10 is not implemented, check the WR bit to see if a write is in progress. 2. Write the address to EEADR. Make sure that the address is not larger than the memory size of the device. 3. Write the 8-bit data value to be programmed in the EEDATA register. 4. Clear the EEPGD bit to point to EEPROM data memory. 5. Set the WREN bit to enable program operations. 6. Disable interrupts (if enabled). 7. Execute the special five instruction sequence: * Write 55h to EECON2 in two steps (first to W, then to EECON2) * Write AAh to EECON2 in two steps (first to W, then to EECON2) * Set the WR bit 8. Enable interrupts (if using interrupts). 9. Clear the WREN bit to disable program operations. 10. At the completion of the write cycle, the WR bit is cleared and the EEIF interrupt flag bit is set. (EEIF must be cleared by firmware.) If step 1 is not implemented, then firmware should check for EEIF to be set, or WR to clear, to indicate the end of the program cycle. 1. To read a data memory location, the user must write the address to the EEADRL register, clear the EEPGD control bit (EECON1<7>), and then set control bit RD (EECON1<0>). The data is available in the very next cycle, in the EEDATL register; therefore, it can be read in the next instruction. EEDATL will hold this value until another read or until it is written to by the user (during a write operation).
EXAMPLE 13-1:
BSF BCF MOVF MOVWF BSF BCF BSF BCF MOVF
DATA EEPROM READ
; ; ; ; ; ; ; ; ; ; Bank 2 Data Memory Address to read Bank 3 Point to Data memory EE Read Bank 2 W = EEDATA
STATUS,RP1 STATUS,RP0 DATA_EE_ADDR,W EEADR STATUS,RP0 EECON1,EEPGD EECON1,RD STATUS,RP0 EEDATA,W
13.1.3
WRITING TO THE DATA EEPROM MEMORY
To write an EEPROM data location, the user must first write the address to the EEADRL register and the data to the EEDATL register. Then the user must follow a specific sequence to initiate the write for each byte. The write will not initiate if the sequence described below is not followed exactly (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. Interrupts should be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software.
EXAMPLE 13-2:
BSF BSF BTFSC GOTO BCF MOVF MOVWF MOVF MOVWF BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF
DATA EEPROM WRITE
STATUS,RP1 ; STATUS,RP0 EECON1,WR ;Wait for write $-1 ;to complete STATUS,RP0 ;Bank 2 DATA_EE_ADDR,W;Data Memory EEADR ;Address to write DATA_EE_DATA,W;Data Memory Value EEDATA ;to write STATUS,RP0 ;Bank 3 EECON1,EEPGD ;Point to DATA ;memory EECON1,WREN ;Enable writes ;Disable INTs. ; ;Write 55h ; ;Write AAh ;Set WR bit to ;begin write INTCON,GIE ;Enable INTs. EECON1,WREN ;Disable writes INTCON,GIE 55h EECON2 AAh EECON2 EECON1,WR
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Required Sequence
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13.1.4 READING THE FLASH PROGRAM MEMORY
To read a program memory location, the user must write two bytes of the address to the EEADRL and EEADRH registers, set the EEPGD control bit (EECON1<7>), and then set control bit RD (EECON1<0>). Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the "BSF EECON1,RD" instruction to be ignored. The data is available in the very next cycle, in the EEDATL and EEDATH registers; therefore, it can be read as two bytes in the following instructions. EEDATL and EEDATH registers will hold this value until another read or until it is written to by the user (during a write operation). Note 1: The two instructions following a program memory read are required to be NOP's. This prevents the user from executing a two-cycle instruction on the next instruction after the RD bit is set. 2: If the WR bit is set when EEPGD = 1, it will be immediately reset to `0' and no operation will take place.
EXAMPLE 13-3:
BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BSF
Required Sequence
FLASH PROGRAM READ
STATUS, RP1 ; STATUS, RP0 ; MS_PROG_EE_ADDR; EEADRH ; LS_PROG_EE_ADDR; EEADR ; STATUS, RP0 ; EECON1, EEPGD ; EECON1, RD ; Bank 2 MS Byte of Program Address to read LS Byte of Program Address to read Bank 3 Point to PROGRAM memory EE Read
; NOP NOP ; BCF MOVF MOVWF MOVF MOVWF STATUS, RP0 EEDATA, W DATAL EEDATH, W DATAH ; Bank 2 ; W = LS Byte of Program EEDATA ; ; W = MS Byte of Program EEDATA ; ; Any instructions here are ignored as program ; memory is read in second cycle after BSF EECON1,RD
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FIGURE 13-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash ADDR
PC
PC + 1
EEADRH,EEADRL
PPC+3 C+3
PC + 4
PC + 5
Flash Data
INSTR (PC)
INSTR (PC + 1)
EEDATH,EEDATL
INSTR (PC + 3)
INSTR (PC + 4)
INSTR(PC - 1) executed here
BSF EECON1,RD executed here
INSTR(PC + 1) executed here
Forced NOP executed here
INSTR(PC + 3) executed here
INSTR(PC + 4) executed here
RD bit
EEDATH EEDATL register
EERHLT
TABLE 13-1:
Addr Name
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Bit 7 GIE EEIF EEIE Bit 6 PEIE ADIF ADIE Bit 5 T0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE SSPIF SSPIE Bit 2 T0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF TMR1IF TMR1IE Value on POR, BOR 0000 000x 0000 0000 0000 0000 0000 0000 0000 0000 --00 0000 Value on all other Resets 0000 000x 0000 0000 0000 0000 0000 0000 0000 0000 --00 0000 ---0 0000 ---- q000 ---- ----
0Bh/8Bh/ INTCON 10Bh 0Ch 8Ch 10Ch 10Dh 10Eh 10Fh 18Ch 18Dh Legend: PIR1 PIE1 EEDATL EEADRL EEDATH EEADRH EECON1 EECON2
EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDATL1 EEDATL0 EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0 -- -- EEPGD -- -- -- EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 -- --
EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---0 0000 -- WRERR WREN WR RD 0--- x000 ---- ----
EEPROM Control Register 2 (not a physical register)
x = unknown, u = unchanged, - = unimplemented read as `0', q = value depends upon condition. Shaded cells are not used by data EEPROM module.
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PIC16F917/916/914/913
14.0 SSP MODULE OVERVIEW
The Synchronous Serial Port (SSP) module is a serial interface used to communicate with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes: * Serial Peripheral Interface (SPITM) * Inter-Integrated Circuit (I2 CTM) An overview of I2C operations and additional information on the SSP module can be found in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023). Refer to Application Note AN578, "Use of the SSP Module in the Multi-Master Environment" (DS00578).
14.1
SPI Mode
This section contains register definitions and operational characteristics of the SPI module. Additional information on the SPI module can be found in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023). The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) - RC4/T1G/SDO/SEG11 * Serial Data In (SDI) - RC7/RX/DT/SDI/SDA/SEG8 * Serial Clock (SCK) - RC6/TX/CK/SCK/SCL/SEG9 Additionally, a fourth pin may be used when in a Slave mode of operation: * Slave Select (SS) - RA5/AN4/C2OUT/SS/SEG5 When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits in the SSPCON register (SSPCON<5:0>) and SSPSTAT<7:6>. These control bits allow the following to be specified: * * * * Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Clock edge (output data on rising/falling edge of SCK) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only)
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Preliminary
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REGISTER 14-1: SSPSTAT - SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0 SMP bit 7 bit 7 SMP: SPITM Data Input Sample Phase bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire) SPI Slave mode: SMP must be cleared when SPI is used in Slave mode I2 CTM mode: This bit must be maintained clear CKE: SPI Clock Edge Select bit SPI mode, CKP = 0: 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK (Microwire alternate) SPI mode, CKP = 1: 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK (Microwire default) I2 C mode: This bit must be maintained clear D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: Stop bit (I2C mode only) This bit is cleared when the SSP module is disabled, or when the Start bit is detected last. SSPEN is cleared. 1 = Indicates that a Stop bit has been detected last (this bit is `0' on Reset) 0 = Stop bit was not detected last S: Start bit (I2C mode only) This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last. SSPEN is cleared. 1 = Indicates that a Start bit has been detected last (this bit is `0' on Reset) 0 = Start bit was not detected last R/W: Read/Write bit Information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or ACK bit. 1 = Read 0 = Write UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2 C mode only): 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 CKE R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 14-2: SSPCON - SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0 WCOL bit 7 bit 7 R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit 0
WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Indicator bit In SPITM mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2 CTM mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don't care" in Transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow
bit 6
bit 5
SSPEN: Synchronous Serial Port Enable bit In SPI mode: 1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output.
bit 4
CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level (Microwire default) 0 = Idle state for clock is a low level (Microwire alternate) In I2 C mode: SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
bit 3-0
SSPM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1011 = I2C Firmware Controlled Master mode (slave idle) 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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FIGURE 14-1: SSP BLOCK DIAGRAM (SPI MODE)
Internal Data Bus Read SSPBUF Reg RC7/RX/ DT/SDI/ SDA/SEG8 SSPSR Reg bit 0 RC4/T1G/ SDO/SEG11 Shift Clock Write
Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: If the SPI is used in Slave mode with CKE = 1, then the SS pin control must be enabled. 3: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), the state of the SS pin can affect the state read back from the TRISC<4> bit. The peripheral OE signal from the SSP module into PORTC controls the state that is read back from the TRISC<4> bit (see Section 19.4 "DC Characteristics: PIC16F917/916/914/913-I (Industrial) PIC16F917/916/914/913-E (Extended)" for information on PORTC). If read-modify-write instructions, such as BSF, are performed on the TRISC register while the SS pin is high, this will cause the TRISC<4> bit to be set, thus disabling the SDO output.
Peripheral OE
SS Control Enable RA5/AN2/ C2OUT/SS/ SEG5 Edge Select 2 Clock Select SSPM<3:0> 4 Edge Select RC6/TX/CK/ SCK/ SCL/ SEG9 TRISC<6> TMR2 Output 2 Prescaler TCY 4, 16, 64
To enable the serial port, SSPEN bit (SSPCON<5>) must be set. To reset or reconfigure SPI mode: * Clear bit SSPEN * Re-initialize the SSPCON register * Set SSPEN bit This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave in a serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed. This is: * SDI must have TRISC<7> set * SDO must have TRISC<4> cleared * SCK (Master mode) must have TRISC<6> cleared * SCK (Slave mode) must have TRISC<6> set * SS must have TRISA<5> set.
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14.2 Operation
When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data Input Sample Phase (middle or end of data output time) * Clock Edge (output data on rising/falling edge of SCK) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) The SSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. Once the eight bits of data have been received, that byte is moved to the SSPBUF register. Then, the Buffer Full detect bit, BF (SSPSTAT<0>), and the interrupt flag bit, SSPIF, are set. This double-buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored and the write collision detect bit, WCOL (SSPCON<7>), will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. * * * * When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. Buffer Full bit, BF (SSPSTAT<0>), indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the SSP interrupt is used to determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 14-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the SSP Status register (SSPSTAT) indicates the various status conditions.
EXAMPLE 14-1:
LOOP BTFSS BRA MOVF MOVWF MOVF MOVWF
LOADING THE SSPBUF (SSPSR) REGISTER
;Has data been received(transmit complete)? ;No ;WREG reg = contents of SSPBUF ;Save in user RAM, if data is meaningful ;W reg = contents of TXDATA ;New data to xmit
SSPSTAT, BF LOOP SSPBUF, W RXDATA TXDATA, W SSPBUF
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14.3 Enabling SPI I/O 14.4 Typical Connection
To enable the serial port, SSP Enable bit, SSPEN (SSPCON<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed. That is: * SDI is automatically controlled by the SPI module * SDO must have TRISC<4> bit cleared * SCK (Master mode) must have TRISC<6> bit cleared * SCK (Slave mode) must have TRISC<6> bit set * SS must have TRISA<5> bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. Figure 14-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission: * Master sends data - Slave sends dummy data * Master sends data - Slave sends data * Master sends dummy data - Slave sends data
FIGURE 14-2:
SPITM MASTER/SLAVE CONNECTION
SPITM Master SSPM<3:0> = 00xxb SDO Serial Input Buffer (SSPBUF) SDI
SPITM Slave SSPM<3:0> = 010xb
Serial Input Buffer (SSPBUF)
Shift Register (SSPSR) MSb LSb
SDI
SDO MSb
Shift Register (SSPSR) LSb
SCK Processor 1
Serial Clock
SCK Processor 2
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14.5 Master Mode
The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 14-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and Status bits appropriately set). This could be useful in receiver applications as a "Line Activity Monitor" mode. The clock polarity is selected by appropriately programming the CKP bit (SSPCON<4>). This then, would give waveforms for SPI communication as shown in Figure 14-3, Figure 14-5 and Figure 14-6, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2
This allows a maximum data rate (at 40 MHz) of 10 Mbps. Figure 14-3 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown.
FIGURE 14-3:
Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) SDO (CKE = 1) SDI (SMP = 0) Input Sample (SMP = 0) SDI (SMP = 1) Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF
SPITM MODE WAVEFORM (MASTER MODE)
4 Clock Modes
bit 7 bit 7
bit 6 bit 6
bit 5 bit 5
bit 4 bit 4
bit 3 bit 3
bit 2 bit 2
bit 1 bit 1
bit 0 bit 0
bit 7
bit 0
bit 7
bit 0
Next Q4 Cycle after Q2
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14.6 Slave Mode
In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. When a byte is received, the device will wake-up from Sleep. becomes a floating output. External pull-up/pull-down resistors may be desirable, depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: If the SPI is used in Slave Mode with CKE set, then the SS pin control must be enabled. When the SPI module resets, the bit counter is forced to `0'. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the SPI needs to operate as a receiver, the SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function) since it cannot create a bus conflict.
14.7
Slave Select Synchronization
The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPCON<3:0> = 04h). The pin must not be driven low for the SS pin to function as an input. The data latch must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte, and
FIGURE 14-4:
SS
SLAVE SYNCHRONIZATION WAVEFORM
SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0)
Write to SSPBUF
SDO
bit 7
bit 6
bit 7
bit 0
SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF
bit 0 bit 7 bit 7
Next Q4 Cycle after Q2
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FIGURE 14-5:
SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF Next Q4 Cycle after Q2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SPITM MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
bit 7
bit 0
FIGURE 14-6:
SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF
SPITM MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 0
Next Q4 Cycle after Q2
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14.8 Sleep Operation 14.10 Bus Mode Compatibility
Table 14-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. In Master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from Sleep. After the device returns to normal mode, the module will continue to transmit/receive data. In Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the SSP interrupt flag bit will be set and if enabled, will wake the device from Sleep.
TABLE 14-1:
SPITM BUS MODES
Control Bits State CKP 0 0 1 1 CKE 1 0 1 0
Standard SPITM Mode Terminology 0, 0 0, 1 1, 0 1, 1
14.9
Effects of a Reset
A Reset disables the SSP module and terminates the current transfer.
There is also a SMP bit which controls when the data is sampled.
TABLE 14-2:
Address
REGISTERS ASSOCIATED WITH SPITM OPERATION
Bit 7 GIE EEIF WCOL TRISC7 EEIE
TRISA7
Name
Bit 6 PEIE ADIF SSPOV TRISC6 ADIE
TRISA6
Bit 5 T0IE RCIF SSPEN TRISC5 RCIE
TRISA5
Bit 4 INTE TXIF CKP TRISC4 TXIE
TRISA4
Bit 3 RBIE SSPIF SSPM3 TRISC3 SSPIE
TRISA3
Bit 2 T0IF CCP1IF SSPM2 TRISC2 CCP1IE
TRISA2
Bit 1 INTF TMR2IF SSPM1 TRISC1 TMR2IE
TRISA1
Bit 0 RBIF TMR1IF SSPM0 TRISC0 TMR1IE
TRISA0
Value on: POR, BOR
Value on all other Resets
0Bh,8Bh. INTCON 10Bh,18Bh 0Ch 13h 14h 87h 8Ch 85h 94h Legend: PIR1 SSPBUF SSPCON TRISC PIE1 TRISA SSPSTAT
0000 000x 0000 000x 0000 0000 0000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000
Synchronous Serial Port Receive Buffer/Transmit Register
SMP
CKE
D/A
P
S
R/W
UA
BF
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the SSP in SPI mode.
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14.11 SSP I2 C Operation
The SSP module in I2C mode, fully implements all slave functions, except general call support, and provides interrupts on Start and Stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the Standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RC6/TX/CK/SCK/SCL/SEG9 pin, which is the clock (SCL), and the RC7/RX/DT/SDI/SDA/SEG8 pin, which is the data (SDA). The SSP module functions are enabled by setting SSP enable bit SSPEN (SSPCON<5>). The SSPCON register allows control of the I2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I2C modes to be selected: I2C Slave mode (7-bit address) I2C Slave mode (10-bit address) I2C Slave mode (7-bit address), with Start and Stop bit interrupts enabled to support Firmware Master mode * I2C Slave mode (10-bit address), with Start and Stop bit interrupts enabled to support Firmware Master mode * I2C Start and Stop bit interrupts enabled to support Firmware Master mode; Slave is idle * * * Selection of any I2C mode with the SSPEN bit set forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits. Pull-up resistors must be provided externally to the SCL and SDA pins for proper operation of the I2C module. Additional information on SSP I2C operation can be found in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023).
FIGURE 14-7:
SSP BLOCK DIAGRAM (I2 CTM MODE)
Internal Data Bus
Read RC6/TX/ CK/SCK/ SCL/SEG9 Shift Clock SSPSR Reg RC7/ RX/DT/ SDI/ SDA/ SEG8 MSb SSPBUF Reg
Write
14.12 Slave Mode
LSb Addr Match
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<7:6> set). The SSP module will override the input state with the output data when required (slave-transmitter). When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register. There are certain conditions that will cause the SSP module not to give this ACK pulse. They include (either or both): a) b) The buffer full bit BF (SSPSTAT<0>) was set before the transfer was received. The overflow bit SSPOV (SSPCON<6>) was set before the transfer was received.
Match Detect
SSPADD Reg Start and Stop bit Detect Set, Reset S, P bits (SSPSTAT reg)
The SSP module has five registers for the I2C operation, which are listed below. SSP Control Register (SSPCON) SSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) SSP Shift Register (SSPSR) - Not directly accessible * SSP Address Register (SSPADD) * * * *
In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. Table 14-3 shows the results of when a data transfer byte is received, given the status of bits BF and SSPOV. The shaded cells show the condition where user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. For high and low times of the I2C specification, as well as the requirements of the SSP module, see Section 19.0 "Electrical Specifications".
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14.12.1 ADDRESSING
Once the SSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: a) b) c) d) The SSPSR register value is loaded into the SSPBUF register. The buffer full bit, BF is set. An ACK pulse is generated. SSP interrupt flag bit, SSPIF (PIR1<3>) is set (interrupt is generated if enabled) on the falling edge of the ninth SCL pulse. The sequence of events for 10-bit address is as follows, with steps 7-9 for slave-transmitter: 1. 2. Receive first (high) byte of address (bits SSPIF, BF and bit UA (SSPSTAT<1>) are set). Update the SSPADD register with second (low) byte of address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of address (bits SSPIF, BF and UA are set). Update the SSPADD register with the first (high) byte of address; if match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive repeated Start condition. Receive first (high) byte of address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF.
3. 4. 5.
6. 7. 8. 9.
In 10-bit Address mode, two address bytes need to be received by the slave (Figure 14-8). The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal `1111 0 A9 A8 0', where A9 and A8 are the two MSbs of the address.
TABLE 14-3:
DATA TRANSFER RECEIVED BYTE ACTIONS
SSPSR SSPBUF Yes No No No Generate ACK Pulse Yes No No No Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes Yes
Status Bits as Data Transfer is Received BF 0 1 1 0 Note: SSPOV 0 0 1 1
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
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PIC16F917/916/914/913
14.12.2 RECEPTION
When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON<6>) is set. This is an error condition due to the user's firmware. An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the status of the byte.
FIGURE 14-8:
I2 CTM WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Receiving Address R/W = 0 ACK Receiving Data D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 ACK Receiving Data ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P
SDA
A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7
SCL
S
8
9
SSPIF (PIR1<3>)
Cleared in software
Bus Master terminates transfer
BF (SSPSTAT<0>)
SSPBUF register is read
SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 171
FIGURE 14-9:
DS41250E-page 172
Clock is held low until update of SSPADD has taken place Receive Second Byte of Address Receive Data Byte Receive Data Byte D7 A7 A6 A5 A4 A3 A2 A1 A0 ACK Clock is held low until update of SSPADD has taken place ACK D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 5 1 2 3 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 4 5 6 7 8 9 P Bus master terminates transfer Cleared in software Cleared in software Cleared in software Dummy read of SSPBUF to clear BF flag SSPOV is set because SSPBUF is still full. ACK is not sent. Cleared by hardware when SSPADD is updated with low byte of address UA is set indicating that SSPADD needs to be updated
SDA
Receive First Byte of Address R/W = 0 ACK 1111 0 A9 A8
SCL
S
1
2
3
4
SSPIF
(PIR1<3>)
Cleared in software
PIC16F917/916/914/913
BF (SSPSTAT<0>)
SSPBUF is written with contents of SSPSR
I2CTM SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS)
Preliminary
Cleared by hardware when SSPADD is updated with high byte of address
SSPOV (SSPCON<6>)
UA (SSPSTAT<1>)
UA is set indicating that the SSPADD needs to be updated
(c) 2005 Microchip Technology Inc.
CKP
(CKP does not reset to `0' when SEN = 0)
PIC16F917/916/914/913
14.12.3 TRANSMISSION
When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit, and pin RC6/TX/CK/SCK/SCL/SEG9 is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then, pin RC6/TX/CK/SCK/SCL/SEG9 should be enabled by setting bit CKP (SSPCON<4>). The master must monitor the SCL pin prior to asserting another clock pulse. The slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 14-10). An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse. As a slave-transmitter, the ACK pulse from the master receiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line was high (not ACK), then the data transfer is complete. When the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave then monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC6/TX/CK/SCK/SCL/SEG9 should be enabled by setting bit CKP.
FIGURE 14-10:
I2 CTM WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
Receiving Address R/W = 1 A1 ACK D7 D6 D5 D4 Transmitting Data D3 D2 D1 D0 ACK
SDA
A7
A6
A5
A4
A3
A2
SCL
S
1 2 Data in sampled
3
4
5
6
7
8
9
1 SCL held low while CPU responds to SSPIF
2
3
4
5
6
7
8
9
P
SSPIF (PIR1<3>) BF (SSPSTAT<0>)
Cleared in software
SSPBUF is written in software CKP (SSPCON<4>)
From SSP Interrupt Service Routine
Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set)
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 173
FIGURE 14-11:
DS41250E-page 174
Bus master terminates transfer ACK 0 A9 A8 ACK ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 D7 D6 D5 D4 D3 D2 D1 D0 5 Sr 6 1 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 2 3 4 5 6 7 8 9 P Cleared in software Cleared in software Cleared in software Dummy read of SSPBUF to clear BF flag Dummy read of SSPBUF to clear BF flag Write of SSPBUF BF flag is clear initiates transmit at the end of the third address sequence Completion of data transmission clears BF flag Cleared by hardware when SSPADD is updated with low byte of address UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address CKP is set in software CKP is automatically cleared in hardware holding SCL low
Clock is held low until Clock is held low until update of SSPADD has update of SSPADD has Clock is held low until taken place taken place CKP is set to `1' R/W = 0 Receive First Byte of Address Receive First Byte of Address R/W = 1 Receive Second Byte of Address Transmitting Data Byte
SDA
1
1
1
1
SCL
S
1
2
3
4
SSPIF
PIC16F917/916/914/913
(PIR1<3>)
I2CTM SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
Preliminary
BF (SSPSTAT<0>)
UA (SSPSTAT<1>)
SSPBUF is written with contents of SSPSR
UA is set indicating that the SSPADD needs to be updated
CKP (SSPCON<4>)
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
14.13 Master Mode
Master mode of operation is supported in firmware using interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the SSP module is disabled. The Stop (P) and Start (S) bits will toggle based on the Start and Stop conditions. Control of the I2C bus may be taken when the P bit is set or the bus is idle and both the S and P bits are clear. In Master mode, the SCL and SDA lines are manipulated by clearing the corresponding TRISC<6:7> bit(s). The output level is always low, irrespective of the value(s) in PORTC<6:7>. So when transmitting data, a `1' data bit must have the TRISC<7> bit set (input) and a `0' data bit must have the TRISC<7> bit cleared (output). The same scenario is true for the SCL line with the TRISC<6> bit. Pull-up resistors must be provided externally to the SCL and SDA pins for proper operation of the I2C module. The following events will cause the SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt will occur if enabled): * Start condition * Stop condition * Data transfer byte transmitted/received Master mode of operation can be done with either the Slave mode idle (SSPM<3:0> = 1011), or with the Slave active. When both Master and Slave modes are enabled, the software needs to differentiate the source(s) of the interrupt.
14.14 Multi-Master Mode
In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions, allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the SSP module is disabled. The Stop (P) and Start (S) bits will toggle based on the Start and Stop conditions. Control of the I2C bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is idle and both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt when the Stop condition occurs. In Multi-Master operation, the SDA line must be monitored to see if the signal level is the expected output level. This check only needs to be done when a high level is output. If a high level is expected and a low level is present, the device needs to release the SDA and SCL lines (set TRISC<6:7>). There are two stages where this arbitration can be lost, these are: * Address Transfer * Data Transfer When the slave logic is enabled, the slave continues to receive. If arbitration was lost during the address transfer stage, communication to the device may be in progress. If addressed, an ACK pulse will be generated. If arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time.
14.14.1
CLOCK SYNCHRONIZATION AND THE CKP BIT
When the CKP bit is cleared, the SCL output is forced to `0'; however, setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 14-12).
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 175
PIC16F917/916/914/913
FIGURE 14-12: CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX
DX-1
SCL Master device asserts clock Master device deasserts clock WR SSPCON
CKP
TABLE 14-4:
Address
REGISTERS ASSOCIATED WITH I2 CTM OPERATION
Bit 7 GIE EEIF EEIE Bit 6 PEIE ADIF ADIE Bit 5 T0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE Bit 2 T0IF Bit 1 INTF Bit 0 RBIF Value on: POR, BOR Value on all other Resets
Name
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 8Ch 13h 14h 87h 93h 94h Legend: Note 1: PIR1 PIE1
0000 000x 0000 000x
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register SSPCON WCOL SSPOV SSPEN TRISC CKP
2CTM
SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 1111 1111 1111 1111
PORTC Data Direction Register mode) Address Register S R/W UA BF
(1)
SSPADD Synchronous Serial Port (I SSPSTAT SMP CKE(1) D/A
0000 0000 0000 0000 0000 0000 0000 0000
P
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by SSP module in I2C mode. Maintain these bits clear in I2C mode.
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Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
15.0 CAPTURE/COMPARE/PWM MODULES
CCP2 Module: Capture/Compare/PWM Register2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. The special event trigger is generated by a compare match and will reset Timer1 and start an A/D conversion (if the A/D module is enabled). Additional information on CCP modules is available in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023) and in Application Note AN594, "Using the CCP Modules" (DS00594).
Each Capture/Compare/PWM (CCP) module contains a 16-bit register which can operate as a: * 16-bit Capture register * 16-bit Compare register * PWM Master/Slave Duty Cycle register Both the CCP1 and CCP2 modules are identical in operation, with the exception being the operation of the special event trigger. Table 15-1 and Table 15-2 show the resources and interactions of the CCP module(s). In the following sections, the operation of a CCP module is described with respect to CCP1. CCP2 operates the same as CCP1, except where noted. CCP1 Module: Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. The special event trigger is generated by a compare match and will reset Timer1.
TABLE 15-1:
CCP MODE - TIMER RESOURCES REQUIRED
Timer Resource Timer1 Timer1 Timer2
CCP Mode Capture Compare PWM
TABLE 15-2:
INTERACTION OF TWO CCP MODULES
Interaction Same TMR1 time base The compare should be configured for the special event trigger, which clears TMR1 The compare(s) should be configured for the special event trigger, which clears TMR1 The PWMs will have the same frequency and update rate (TMR2 interrupt) None None
CCPx Mode CCPy Mode Capture Capture Compare PWM PWM PWM Capture Compare Compare PWM Capture Compare
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 177
PIC16F917/916/914/913
REGISTER 15-1: CCP1CON - CCP2CON(1) REGISTER (ADDRESS: 17h/1Dh)
U-0 -- bit 7 bit 7-6 bit 5-4 Unimplemented: Read as `0' CCPxX:CCPxY: PWM Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. CCPxM<3:0>: CCPx Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCPxIF bit is set) 1001 = Compare mode, clear output on match (CCPxIF bit is set) 1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected) 1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx = PWM mode Note 1: CCP2CON used for PIC16F914/917 only. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 CCPxX R/W-0 CCPxY R/W-0 CCPxM3 R/W-0 CCPxM2 R/W-0 CCPxM1 R/W-0 CCPxM0 bit 0
bit 3-0
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Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
15.1 Capture Mode
15.1.4 CCP PRESCALER
In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC5/T1CKI/CCP1/SEG10. An event is defined as one of the following: * * * * Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge There are four prescaler settings, specified by bits CCP1M<3:0>. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. Example 15-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt.
The type of event is configured by control bits CCP1M<3:0> (CCPxCON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. The interrupt flag must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value is overwritten by the new value.
EXAMPLE 15-1:
CLRF MOVLW
CHANGING BETWEEN CAPTURE PRESCALERS
15.1.1
CCP PIN CONFIGURATION
In Capture mode, the RC5/T1CKI/CCP1/SEG10 pin should be configured as an input by setting the TRISC<5> bit. Note: If the RC5/T1CKI/CCP1/SEG10 pin is configured as an output, a write to the port can cause a capture condition.
MOVWF
CCP1CON ; Turn CCP module off NEW_CAPT_PS ; Load the W reg with ; the new prescaler ; move value and CCP ON CCP1CON ; Load CCP1CON with this ; value
FIGURE 15-3:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set Flag bit CCP1IF (PIR1<2>)
RC5/T1CKI/ CCP1/SEG10 pin
Prescaler / 1, 4, 16
CCPR1H and edge detect Capture Enable TMR1H CCP1CON<3:0> Qs
CCPR1L
TMR1L
15.1.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode, or Synchronized Counter mode, for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work.
15.1.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit CCP1IF, following any such change in Operating mode.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 179
PIC16F917/916/914/913
15.2 Compare Mode
15.2.3 SOFTWARE INTERRUPT MODE
In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC5/T1CKI/CCP1/SEG10 pin is: * Driven high * Driven low * Remains unchanged The action on the pin is based on the value of control bits CCP1M<3:0> (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF is set. When Generate Software Interrupt mode is chosen, the RC5/T1CKI/CCP1/SEG10 pin is not affected. The CCPIF bit is set, causing a CCP interrupt (if enabled).
15.2.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated, which may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. The special event trigger output of CCP2 resets the TMR1 register pair and starts an A/D conversion (if the A/D module is enabled). Note: The special event trigger from the CCP1 and CCP2 modules will not set interrupt flag bit TMR1IF (PIR1<0>).
FIGURE 15-4:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/DONE (ADCON0<2>). Special Event Trigger Set Flag bit CCP1IF (PIR1<2>) CCPR1H CCPR1L Q S R TRISC<5> Output Enable Output Logic Comparator TMR1H TMR1L
15.3
PWM Mode (PWM)
RC5/T1CKI/ CCP1/SEG10 pin
Match
In Pulse Width Modulation mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the RC5/T1CKI/CCP1/SEG10 pin is multiplexed with the PORTC data latch, the TRISC<5> bit must be cleared to make the RC5/T1CKI/CCP1/SEG10 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch.
CCP1CON<3:0> Mode Select
15.2.1
CCP PIN CONFIGURATION
The user must configure the RC5/T1CKI/CCP1/SEG10 pin as an output by clearing the TRISC<5> bit. Note: Clearing the CCP1CON register will force the RC5/T1CKI/CCP1/SEG10 compare output latch to the default low level. This is not the PORTC I/O data latch.
Figure 15-5 shows a simplified block diagram of the CCP module in PWM mode. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 15.3.3 "Setup for PWM Operation".
15.2.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode, or Synchronized Counter mode, if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work.
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Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
FIGURE 15-5: SIMPLIFIED PWM BLOCK DIAGRAM
CCP1CON<5:4>
When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The RC5/T1CKI/CCP1/SEG10 pin is set (exception: if PWM duty cycle = 0%, the RC5/T1CKI/CCP1/SEG10 pin will not be set) * The PWM duty cycle is latched from CCPR1L into CCPR1H
Duty Cycle Registers CCPR1L
CCPR1H (Slave)
RC5/T1CKI/ CCP1/SEG10 R Q
Note:
Comparator
TMR2
(1) S
The Timer2 postscaler (see Section 7.0 "Timer2 Module") is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output.
Comparator Clear Timer, CCP1 pin and latch D.C.
TRISC<5>
15.3.2
PWM DUTY CYCLE
PR2
Note
1:
The 8-bit timer is concatenated with 2-bit internal Q clock, or 2 bits of the prescaler, to create 10-bit time base.
A PWM output (Figure 15-6) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time: PWM duty cycle =(CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 prescale value) CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitch-free PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock, or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the formula:
FIGURE 15-6:
Period
PWM OUTPUT
Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2
15.3.1
PWM PERIOD
The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: PWM period = (PR2) + 1] * 4 * TOSC * (TMR2 prescale value) PWM frequency is defined as 1/[PWM period].
FOSC log ------------------------------------------------------------- FPWM x TMR2 Prescaler PWM Resolution = ---------------------------------------------------------------------------bits log ( 2 ) Note: If the PWM duty cycle value is longer than the PWM period, the RC5/T1CKI/CCP1/SEG10 pin will not be cleared.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 181
PIC16F917/916/914/913
15.3.3 SETUP FOR PWM OPERATION
The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. 4. 5. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the RC5/T1CKI/CCP1/SEG10 pin an output by clearing the TRISC<5> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation.
TABLE 15-1:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
1.22 kHz 16 0xFFh 10 4.88 kHz 4 0xFFh 10 19.53 kHz 1 0xFFh 10 78.12kHz 1 0x3Fh 8 156.3 kHz 1 0x1Fh 7 208.3 kHz 1 0x17h 5.5
PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits)
TABLE 15-2:
Address
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Bit 7 GIE EEIF OSFIF EEIE OSFIE TRISC7 Bit 6 PEIE ADIF C2IF ADIE C2IE TRISC6 Bit 5 T0IE RCIF C1IF RCIE C1IE TRISC5 Bit 4 INTE TXIF LCDIF TXIE LCDIE TRISC4 Bit 3 RBIE SSPIF -- SSPIE -- TRISC3 Bit 2 T0IF CCP1IF LVDIF CCP1IE LVDIE TRISC2 Bit 1 INTF TMR2IF -- TMR2IE -- TRISC1 Bit 0 RBIF TMR1IF CCP2IF TMR1IE CCP2IE TRISC0 Value on: POR, BOR Value on all other Resets
Name
0Bh,8Bh, INTCON 10Bh, 18Bh 0Ch 0Dh 8Ch 8Dh 87h 0Eh 0Fh 10h 15h 16h 17h 1Bh 1Ch 1Dh Legend: PIR1 PIR2 PIE1 PIE2 TRISC TMR1L TMR1H T1CON CCPR1L CCPR1H CCP1CON CCPR2L CCPR2H CCP2CON
0000 000x 0000 000x 0000 0000 0000 0000 0000 -0-0 0000 -0-0 0000 0000 0000 0000 0000 -0-0 0000 -0-0 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register T1GINV T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0000 0000 uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) -- -- CCP1X CCP1Y CCP1M3
CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register 2 (LSB) Capture/Compare/PWM Register 2 (MSB) -- -- CCP2X CCP2Y CCP2M3
CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by Capture and Timer1.
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TABLE 15-3:
Address Name
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Bit 7 GIE EEIF OSFIF EEIE OSFIE Bit 6 PEIE ADIF C2IF ADIE C2IE Bit 5 T0IE RCIF C1IF RCIE C1IE Bit 4 INTE TXIF LCDIF TXIE LCDIE Bit 3 RBIE SSPIF -- SSPIE -- Bit 2 T0IF CCP1IF LVDIF CCP1IE LVDIE Bit 1 INTF TMR2IF -- TMR2IE -- Bit 0 RBIF TMR1IF CCP2IF TMR1IE CCP2IE Value on: POR, BOR Value on all other Resets
0Bh,8Bh, INTCON 10Bh, 18Bh 0Ch 0Dh 8Ch 8Dh 87h 11h 92h 12h 15h 16h 17h 1Bh 1Ch 1Dh Legend: PIR1 PIR2 PIE1 PIE2 TRISC TMR2 PR2 T2CON CCPR1L CCPR1H CCP1CON CCPR2L CCPR2H CCP2CON
0000 000x 0000 000x 0000 0000 0000 0000 0000 -0-0 0000 -0-0 0000 0000 0000 0000 0000 -0-0 0000 -0-0 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111
PORTC Data Direction Register Timer2 Module Register Timer2 Module Period Register --
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) -- -- CCP1X CCP1Y
Capture/Compare/PWM Register 2 (LSB) Capture/Compare/PWM Register 2 (MSB) -- -- CCP2X CCP2Y
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by PWM and Timer2.
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NOTES:
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16.0 SPECIAL FEATURES OF THE CPU
The PIC16F917/916/914/913 has two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 64 ms (nominal) on power-up only, designed to keep the part in Reset while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs, which can use the Power-up Timer to provide at least a 64 ms Reset. With these three functions-on-chip, most applications need no external Reset circuitry. The Sleep mode is designed to offer a very low-current Power-down mode. The user can wake-up from Sleep through: * External Reset * Watchdog Timer Wake-up * An interrupt Several oscillator options are also made available to allow the part to fit the application. The INTOSC option saves system cost, while the LP crystal option saves power. A set of configuration bits are used to select various options (see Register 16-1).
The PIC16F917/916/914/913 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection. These features are: * Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * Oscillator Selection * Sleep * Code Protection * ID Locations * In-Circuit Serial ProgrammingTM
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PIC16F917/916/914/913
16.1 Configuration Bits
Note: Address 2007h is beyond the user program memory space. It belongs to the special configuration memory space (2000h-3FFFh), which can be accessed only during programming. See "PIC16F917/916/914/913 Memory Programming Specification" (DS41244) for more information. The configuration bits can be programmed (read as `0'), or left unprogrammed (read as `1') to select various device configurations as shown in Register 16-1. These bits are mapped in program memory location 2007h.
REGISTER 16-1:
-- bit 13 DEBUG
CONFIG - CONFIGURATION WORD (ADDRESS: 2007h)
IESO BOREN1 BOREN0 CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 bit 0
FCMEN
bit 13 bit 12
Unimplemented: Read as `1' DEBUG: In-Circuit Debugger Mode bit 1 = In-Circuit Debugger disabled, RB6/ICSPCLK/ICDCK/SEG14 and RB7/ICSPDAT/ICDDAT/SEG13 are general purpose I/O pins 0 = In-Circuit Debugger enabled, RB6/ICSPCLK/ICDCK/SEG14 and RB7/ICSPDAT/ICDDAT/SEG13 are dedicated to the debugger FCMEN: Fail-Safe Clock Monitor Enabled bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled IESO: Internal External Switchover bit 1 = Internal External Switchover mode is enabled 0 = Internal External Switchover mode is disabled BOREN<1:0>: Brown-out Reset Selection bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit (PCON<4>) 00 = BOR disabled CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled CP: Code Protection bit(3) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled MCLRE: RB3/MCLR/VPP pin function select bit(4) 1 = RB3/MCLR/VPP pin function is MCLR 0 = RB3/MCLR/VPP pin function is digital input, MCLR internally tied to VDD PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled and can be enabled by SWDTEN bit (WDTCON<0>) FOSC<2:0>: Oscillator Selection bits 111 = RC oscillator: CLKO function on RA6/OSC2/CLKO/T1OSO pin, RC on RA7/OSC1/CLKI/T1OSI 110 = RCIO oscillator: I/O function on RA6/OSC2/CLKO/T1OSO pin, RC on RA7/OSC1/CLKI/T1OSI 101 = INTOSC oscillator: CLKO function on RA6/OSC2/CLKO/T1OSO pin, I/O function on RA7/OSC1/CLKI/T1OSI 100 = INTOSCIO oscillator: I/O function on RA6/OSC2/CLKO/T1OSO pin, I/O function on RA7/OSC1/CLKI/T1OSI 011 = EC: I/O function on RA6/OSC2/CLKO/T1OSO pin, CLKI on RA7/OSC1/CLKI/T1OSI 010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKO/T1OSO and RA7/OSC1/CLKI/T1OSI 001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKO/T1OSO and RA7/OSC1/CLKI/T1OSI 000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKO/T1OSO and RA7/OSC1/CLKI/T1OSI Note 1: 2: 3: 4: Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire data EEPROM will be erased when the code protection is turned off. The entire program memory will be erased when the code protection is turned off. When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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16.2 Reset
The PIC16F917/916/914/913 differentiates between various kinds of Reset: a) b) c) d) e) f) Power-on Reset (POR) WDT Reset during normal operation WDT Reset during Sleep MCLR Reset during normal operation MCLR Reset during Sleep Brown-out Reset (BOR) They are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 16-2. These bits are used in software to determine the nature of the Reset. See Table 16-5 for a full description of Reset states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 16-1. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section 19.0 "Electrical Specifications" for pulse width specifications.
Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a "Reset state" on: * * * * * Power-on Reset MCLR Reset MCLR Reset during Sleep WDT Reset Brown-out Reset (BOR)
FIGURE 16-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR/VPP pin SLEEP WDT Module VDD Rise Detect VDD Brown-out(1) Reset Power-on Reset BOREN SBOREN WDT Time-out Reset
S
OST/PWRT OST 10-bit Ripple Counter OSC1/ CLKI pin PWRT LFINTOSC 11-bit Ripple Counter R Q Chip_Reset
Enable PWRT Enable OST
Note
1:
Refer to the Configuration Word register (Register 16-1).
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Preliminary
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PIC16F917/916/914/913
16.3 Power-on Reset
FIGURE 16-2:
VDD R1 1 k (or greater) PIC16F917/916/ 914/913
The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Section 19.0 "Electrical Specifications" for details. If the BOR is enabled, the maximum rise time specification does not apply. The BOR circuitry will keep the device in Reset until VDD reaches VBOR (see Section 16.3.3 "Brown-Out Reset (BOR)"). Note: The POR circuit does not produce an internal Reset when VDD declines. To re-enable the POR, VDD must reach Vss for a minimum of 100 s.
RECOMMENDED MCLR CIRCUIT
MCLR C1 0.1 F (optional, not critical)
16.3.2
POWER-UP TIMER (PWRT)
When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting" (DS00607).
The Power-up Timer provides a fixed 64 ms (nominal) time-out on power-up only, from POR or Brown-out Reset. The Power-up Timer operates from the 31 kHz LFINTOSC oscillator. For more information, see Section 4.4 "Internal Clock Modes". The chip is kept in Reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A configuration bit, PWRTE, can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer should be enabled when Brown-out Reset is enabled, although it is not required. The Power-up Timer delay will vary from chip-to-chip and vary due to: * VDD variation * Temperature variation * Process variation See DC parameters for details "Electrical Specifications"). (Section 19.0
16.3.1
MCLR
PIC16F917/916/914/913 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from early devices of this family. Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 16-2, is suggested. An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When cleared, MCLR is internally tied to VDD and an internal weak pull-up is enabled for the MCLR pin. In-Circuit Serial Programming is not affected by selecting the internal MCLR option.
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16.3.3 BROWN-OUT RESET (BOR)
The BOREN0 and BOREN1 bits in the Configuration Word register selects one of four BOR modes. Two modes have been added to allow software or hardware control of the BOR enable. When BOREN<1:0> = 01, the SBOREN bit (PCON<4>) enables/disables the BOR allowing it to be controlled in software. By selecting BOREN<1:0>, the BOR is automatically disabled in Sleep to conserve power and enabled on wake-up. In this mode, the SBOREN bit is disabled. See Register 16-1 for the configuration word definition. If VDD falls below VBOR for greater than parameter (TBOR) (see Section 19.0 "Electrical Specifications"), the Brown-out situation will reset the device. This will occur regardless of VDD slew rate. A Reset is not insured to occur if VDD falls below VBOR for less than parameter (TBOR). On any Reset (Power-on, Brown-out Reset, Watchdog Timer, etc.), the chip will remain in Reset until VDD rises above VBOR (see Figure 16-3). The Power-up Timer will now be invoked, if enabled and will keep the chip in Reset an additional 64 ms. Note: The Power-up Timer is enabled by the PWRTE bit in the Configuration Word. If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once VDD rises above VBOR, the Power-up Timer will execute a 64 ms Reset.
16.3.4
BOR CALIBRATION
The PIC16F917/916/914/913 stores the BOR calibration values in fuses located in the Calibration Word (2008h). The Calibration Word is not erased when using the specified bulk erase sequence in the "PIC16F917/916/914/913 Memory Programming Specification" (DS41244) and thus, does not require reprogramming. Address 2008h is beyond the user program memory space. It belongs to the special configuration memory space (2000h-3FFFh), which can be accessed only during programming. See "PIC16F917/916/914/913 Memory Programming Specification" (DS41244) for more information.
FIGURE 16-3:
VDD
BROWN-OUT SITUATIONS
VBOR
Internal Reset VDD
64 ms(1)
VBOR < 64 ms
Internal Reset
64 ms(1)
VDD
VBOR
Internal Reset Note 1: 64 ms delay only if PWRTE bit is programmed to `0'.
64 ms(1)
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16.3.5 TIME-OUT SEQUENCE 16.3.6
On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR has expired, then OST is activated after the PWRT time-out has expired. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 16-4, Figure 16-5 and Figure 16-6 depict time-out sequences. The device can execute code from the INTOSC while OST is active, by enabling Two-Speed Start-up or Fail-Safe Monitor (see Section 4.6.2 "Two-Speed Start-up Sequence" and Section 4.7 "Fail-Safe Clock Monitor"). Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then, bringing MCLR high will begin execution immediately (see Figure 16-5). This is useful for testing purposes or to synchronize more than one PIC16F917/916/914/913 device operating in parallel. Table 16-5 shows the Reset conditions for some special registers, while Table 16-5 shows the Reset conditions for all the registers.
POWER CONTROL (PCON) REGISTER
The Power Control (PCON) register (address 8Eh) has two Status bits to indicate what type of Reset that last occurred. Bit 0 is BOR (Brown-out Reset). BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent Resets to see if BOR = 0, indicating that a Brown-out has occurred. The BOR Status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (BOREN<1:0> = 00 in the Configuration Word register). Bit 1 is POR (Power-on Reset). It is a `0' on Power-on Reset and unaffected otherwise. The user must write a `1' to this bit following a Power-on Reset. On a subsequent Reset, if POR is `0', it will indicate that a Power-on Reset has occurred (i.e., VDD may have gone too low). For more information, see Section 16.3.3 "Brown-Out Reset (BOR)".
TABLE 16-1:
TIME-OUT IN VARIOUS SITUATIONS
Power-up Brown-out Reset PWRTE = 0 TPWRT + 1024 * TOSC TPWRT PWRTE = 1 1024 * TOSC -- Wake-up from Sleep 1024 * TOSC --
Oscillator Configuration PWRTE = 0 XT, HS, LP(1) TPWRT + 1024 * TOSC TPWRT PWRTE = 1 1024 * TOSC --
RC, EC, INTOSC Note 1:
LP mode with T1OSC disabled.
TABLE 16-2:
POR 0 1 u u u u u 0 u u u u
PCON BITS AND THEIR SIGNIFICANCE
TO 1 1 0 0 u 1 PD 1 1 u 0 u 0 Power-on Reset Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during Sleep Condition
BOR
Legend: u = unchanged, x = unknown
TABLE 16-3:
Address 03h 8Eh Legend: Note 1: Name
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Bit 7 IRP -- Bit 6 RP1 -- Bit 5 RPO -- Bit 4 TO SBOREN Bit 3 PD -- Bit 2 Z -- Bit 1 DC POR Bit 0 C BOR Value on POR, BOR 0001 1xxx --01 --qq Value on all other Resets(1) 000q quuu --0u --uu
STATUS PCON
u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. Shaded cells are not used by BOR. Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
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FIGURE 16-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1
VDD MCLR Internal POR TPWRT PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 16-5:
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2
VDD MCLR Internal POR TPWRT PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 16-6:
TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD): CASE 3
VDD MCLR Internal POR TPWRT PWRT Time-out
TOST
OST Time-out
Internal Reset
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TABLE 16-4:
Register
INITIALIZATION CONDITION FOR REGISTERS
Address Power-on Reset xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ---- xxxx ---0 0000 0000 000x 0000 0000 0000 -0-0 xxxx xxxx xxxx xxxx 0000 0000 01-0 0-00 -000 0000 xxxx xxxx 0000 0000 0000 0000 0000 0010 000x 000x ---0 1000 0000 0000 0000 0000 --00 0000 xxxx xxxx * MCLR Reset * WDT Reset * Brown-out Reset(1) uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 000q quuu(4) uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 ---- 0000 ---0 0000 0000 000x 0000 0000 0000 -0-0 uuuu uuuu uuuu uuuu uuuu uuuu 01-0 0-00 -000 0000 xxxx xxxx 0000 0000 0000 0000 0000 0010 000x 000x ---0 1000 0000 0000 0000 0000 --00 0000 uuuu uuuu * Wake-up from Sleep through interrupt * Wake-up from Sleep through WDT time-out uuuu uuuu uuuu uuuu uuuu uuuu PC + 1(3) uuuq quuu(4) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu ---u uuuu uuuu uuuu(2) uuuu uuuu(2) uuuu -u-u uuuu uuuu uuuu uuuu uuuu uuuu uu-u u-uu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu
W INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCP2CON ADRESH Legend: Note 1: 2: 3: 4: 5:
-- 00h/80h/ 100h/180h 01h/101h 02h/82h/ 102h/182h 03h/83h/ 103h/183h 04h/84h/ 104h/184h 05h 06h/106h 07h 08h 09h 0Ah/8Ah/ 10Ah/18Ah 0Bh/8Bh/ 10Bh/18Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Dh 1Eh
u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 16-5 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
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TABLE 16-4:
Register
INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Address Power-on Reset 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 --01 --0x -110 q000 ---0 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 0000 ------- --10 0000 -010 0000 0000 0000 0000 0-0- 0000 xxxx xxxx -000 ------0 1000 0001 0011 0000 0000 --00 -100 0000 0000 0000 0000 --00 0000 ---0 0000 xxxx xxxx xxxx xxxx xxxx xxxx * MCLR Reset * WDT Reset * Brown-out Reset(1) 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 --0u --uu(1,5) -110 x000 ---u uuuu 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 0000 ------- --10 0000 -010 0000 0000 0000 0000 0-0- 0000 uuuu uuuu -000 ------0 1000 0001 0011 0000 0000 --00 -100 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu * Wake-up from Sleep through interrupt * Wake-up from Sleep through WDT time-out uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu --uu -uuu uuuu ---u uuuu uuuu uuuu 1111 1111 uuuu uuuu uuuu uuuu uuuu uuuu uuuu ------- --uu uuuu -uuu uuuu uuuu uuuu uuuu u-u- uuuu uuuu uuuu -uuu ------u uuuu uuuu uuuu uuuu uuuu --uu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
ADCON0 OPTION_REG TRISA TRISB TRISC TRISD TRISE PIE1 PIE2 PCON OSCCON OSCTUNE ANSEL PR2 SSPADD SSPSTAT WPUB IOCB CMCON1 TXSTA SPBRG CMCON0 VRCON ADRESL ADCON1 WDTCON LCDCON LCDPS LVDCON EEDATL EEADRL EEDATH EEADRH LCDDATA0 LCDDATA1 LCDDATA2 Legend: Note 1: 2: 3: 4: 5:
1Fh 81h/181h 85h 86h/186h 87h 88h 89h 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ch 9Dh 9Eh 9Fh 105h 107h 108h 109h 10Ch 10Dh 10Eh 10Fh 110h 111h 112h
u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 16-5 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
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TABLE 16-4:
Register
INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Address Power-on Reset xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 x--- x000 * MCLR Reset * WDT Reset * Brown-out Reset(1) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u--- q000 * Wake-up from Sleep through interrupt * Wake-up from Sleep through WDT time-out uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u--- uuuu
LCDDATA3 LCDDATA4 LCDDATA5 LCDDATA6 LCDDATA7 LCDDATA8 LCDDATA9 LCDDATA10 LCDDATA11 LCDSE0 LCDSE1 LCDSE2 EECON1 Legend: Note 1: 2: 3: 4: 5:
113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 18Ch
u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 16-5 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
TABLE 16-5:
INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Condition Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1
(1)
Status Register 0001 1xxx 000u uuuu 0001 0uuu 0000 uuuu uuu0 0uuu 0001 1uuu uuu1 0uuu
PCON Register --01 --0x --0u --uu --0u --uu --0u --uu --uu --uu --01 --10 --uu --uu
Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up Brown-out Reset Interrupt Wake-up from Sleep
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
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PIC16F917/916/914/913
16.4 Interrupts
The PIC16F917/916/914/913 has multiple sources of interrupt: * * * * * * * * * * * * * External Interrupt RB0/INT/SEG0 TMR0 Overflow Interrupt PORTB Change Interrupts 2 Comparator Interrupts A/D Interrupt Timer1 Overflow Interrupt EEPROM Data Write Interrupt Fail-Safe Clock Monitor Interrupt LCD Interrupt PLVD Interrupt USART Receive and Transmit interrupts CCP1 and CCP2 Interrupts TMR2 Interrupt The following interrupt flags are contained in the PIR2 register: * * * * * Fail-Safe Clock Monitor Interrupt Comparator 1 and 2 Interrupts LCD Interrupt PLVD Interrupt CCP2 Interrupt
When an interrupt is serviced: * The GIE is cleared to disable any further interrupt. * The return address is pushed onto the stack. * The PC is loaded with 0004h. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs (see Figure 16-8). The latency is the same for one or two-cycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. Note 1: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. 2: When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The interrupts, which were ignored, are still pending to be serviced when the GIE bit is set again. For additional information on Timer1, A/D or data EEPROM modules, refer to the respective peripheral section. Note: The ANSEL (91h) and CMCON0 (9Ch) registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'. Also, if a LCD output function is active on an external interrupt pin, that interrupt function will be disabled.
The Interrupt Control (INTCON) register and Peripheral Interrupt Request 1 (PIR1) register record individual interrupt requests in flag bits. The INTCON register also has individual and global interrupt enable bits. A Global Interrupt Enable bit, GIE (INTCON<7>), enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in the INTCON register and PIE1 register. GIE is cleared on Reset. The Return from Interrupt instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables unmasked interrupts. The following interrupt flags are contained in the INTCON register: * INT Pin Interrupt * PORTB Change Interrupt * TMR0 Overflow Interrupt The peripheral interrupt flags are contained in the special registers, PIR1 and PIR2. The corresponding interrupt enable bit are contained in the special registers, PIE1 and PIE2. The following interrupt flags are contained in the PIR1 register: * * * * * * EEPROM Data Write Interrupt A/D Interrupt USART Receive and Transmit Interrupts Timer1 Overflow Interrupt CCP1 Interrupt SSP Interrupt
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16.4.1 RB0/INT/SEG0 INTERRUPT 16.4.2 TMR0 INTERRUPT
External interrupt on RB0/INT/SEG0 pin is edge-triggered; either rising if the INTEDG bit (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT/SEG0 pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>). The INTF bit must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt. The RB0/INT/SEG0 interrupt can wake-up the processor from Sleep if the INTE bit was set prior to going into Sleep. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up (0004h). See Section 16.7 "Power-Down Mode (Sleep)" for details on Sleep and Figure 16-10 for timing of wake-up from Sleep through RB0/INT/SEG0 interrupt. An overflow (FFh 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. See Section 5.0 "Timer0 Module" for operation of the Timer0 module.
16.4.3
PORTB INTERRUPT
An input change on PORTB change sets the RBIF (INTCON<0>) bit. The interrupt can be enabled/disabled by setting/clearing the RBIE (INTCON<3>) bit. Plus, individual pins can be configured through the IOCB register. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set.
FIGURE 16-7:
IOC-RB4 IOCB4 IOC-RB5 IOCB5 IOC-RB6 IOCB6 IOC-RB7 IOCB7 TMR2IF TMR2IE TMR1IF TMR1IE C1IF C1IE C2IF C2IE ADIF ADIE OSFIF OSFIE EEIF EEIE CCP1IF CCP1IE CCP2IF CCP2IE RCIF RCIE TXIF TXIE SSPIF SSPIE LCDIF LCDIE LVDIF LVDIE
INTERRUPT LOGIC
TMR0IF TMR0IE INTF INTE RBIF RBIE PEIF PEIE GIE
Wake-up (If in Sleep mode)
Interrupt to CPU
*
* Only available on the PIC16F914/917.
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FIGURE 16-8:
Q1 OSC1 CLKO(3)
(4)
INT PIN INTERRUPT TIMING
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
INT pin INTF Flag (INTCON<1>) GIE bit (INTCON<7>) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: 5:
(1) (5)
(1)
Interrupt Latency (2)
PC Inst (PC) Inst (PC - 1)
PC + 1 Inst (PC + 1) Inst (PC)
PC + 1 -- Dummy Cycle
0004h Inst (0004h) Dummy Cycle
0005h Inst (0005h) Inst (0004h)
INTF flag is sampled here (every Q1). Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. CLKO is available only in INTOSC and RC Oscillator modes. For minimum width of INT pulse, refer to AC specifications in Section 19.0 "Electrical Specifications". INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 16-6:
Addr 0Bh, 8Bh 0Ch 0Dh 8Ch 8Dh Name INTCON PIR1 PIR2 PIE1 PIE2
SUMMARY OF INTERRUPT REGISTERS
Bit 7 GIE EEIF OSFIF EEIE OSFIE Bit 6 PEIE ADIF C2IF ADIE C2IE Bit 5 T0IE RCIF C1IF RCIE C1IE Bit 4 INTE TXIF LCDIF TXIE LCDIE Bit 3 RBIE SSPIF -- SSPIE -- Bit 2 T0IF CCP1IF LVDIF LVDIE Bit 1 INTF Bit 0 RBIF Value on POR, BOR Value on all other Resets
0000 000x 0000 000x
TMR2IF TMR1IF 0000 0000 0000 0000 -- -- CCP2IF 0000 -0-0 0000 -0-0 CCP2IE 0000 -0-0 0000 -0-0
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as `0', q = value depends upon condition. Shaded cells are not used by the interrupt module.
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16.5 Context Saving During Interrupts
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and Status registers). This must be implemented in software. Since the lower 16 bytes of all banks are common in the PIC16F917/916/914/913 (see Figure 2-3), temporary holding registers, W_TEMP and STATUS_TEMP, should be placed in here. These 16 locations do not require banking and therefore, make it easier to context save and restore. The same code shown in Example 16-1 can be used to: * * * * * Store the W register Store the Status register Execute the ISR code Restore the Status (and Bank Select Bit register) Restore the W register
Note:
The PIC16F917/916/914/913 normally does not require saving the PCLATH. However, if computed GOTO's are used in the ISR and the main code, the PCLATH must be saved and restored in the ISR.
EXAMPLE 16-1:
MOVWF SWAPF CLRF MOVWF : :(ISR) : SWAPF MOVWF SWAPF SWAPF
SAVING STATUS AND W REGISTERS IN RAM
;Copy ;Swap ;bank ;Save W to TEMP register status to be saved into W 0, regardless of current bank, Clears IRP,RP1,RP0 status to bank zero STATUS_TEMP register
W_TEMP STATUS,W STATUS STATUS_TEMP
;Insert user code here STATUS_TEMP,W STATUS W_TEMP,F W_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into Status register ;Swap W_TEMP ;Swap W_TEMP into W
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16.6 Watchdog Timer (WDT)
For PIC16F917/916/914/913, the WDT has been modified from previous PIC16F devices. The new WDT is code and functionally compatible with previous PIC16F WDT modules and adds a 16-bit prescaler to the WDT. This allows the user to have a scaled value for the WDT and TMR0 at the same time. In addition, the WDT time-out value can be extended to 268 seconds. WDT is cleared under certain conditions described in Table 16-7. A new prescaler has been added to the path between the INTOSC and the multiplexers used to select the path for the WDT. This prescaler is 16 bits and can be programmed to divide the INTOSC by 32 to 65536, giving the WDT a nominal range of 1 ms to 268s.
16.6.2
WDT CONTROL
The WDTE bit is located in the Configuration Word register. When set, the WDT runs continuously. When the WDTE bit in the Configuration Word register is set, the SWDTEN bit (WDTCON<0>) has no effect. If WDTE is clear, then the SWDTEN bit can be used to enable and disable the WDT. Setting the bit will enable it and clearing the bit will disable it. The PSA and PS<2:0> bits (OPTION_REG) have the same function as in previous versions of the PIC16F family of microcontrollers. See Section 5.0 "Timer0 Module" for more information.
16.6.1
WDT OSCILLATOR
The WDT derives its time base from the 31 kHz LFINTOSC. The LTS bit does not reflect that the LFINTOSC is enabled. The value of WDTCON is `---0 1000' on all Resets. This gives a nominal time base of 16 ms, which is compatible with the time base generated with previous PIC16F microcontroller versions. Note: When the Oscillator Start-up Timer (OST) is invoked, the WDT is held in Reset, because the WDT Ripple Counter is used by the OST to perform the oscillator delay count. When the OST count has expired, the WDT will begin counting (if enabled).
FIGURE 16-9:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source 0 Prescaler(1) 16-bit WDT Prescaler 1 8 PSA
PS<2:0> To TMR0 0 1 PSA
31 kHz LFINTOSC Clock
WDTPS<3:0>
WDTE from Configuration Word register SWDTEN from WDTCON WDT Time-out
Note 1: This is the shared Timer0/WDT prescaler. See Section 5.4 "Prescaler" for more information.
TABLE 16-7:
WDTE = 0
WDT STATUS
Conditions WDT
CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP
Cleared
Cleared until the end of OST
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REGISTER 16-2: WDTCON - WATCHDOG TIMER CONTROL REGISTER (ADDRESS: 105h)
U-0 -- bit 7 bit 7-5 bit 4-1 Unimplemented: Read as `0' WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 (Reset value) 0101 = 1:1024 0110 = 1:2048 0111 = 1:4096 1000 = 1:8192 1001 = 1:16384 1010 = 1:32768 1011 = 1:65536 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved SWDTEN: Software Enable or Disable the Watchdog Timer bit(1) 1 = WDT is turned on 0 = WDT is turned off (Reset value) Note 1: If WDTE configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTE configuration bit = 0, then it is possible to turn WDT on/off with this control bit. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 WDTPS3 R/W-1 WDTPS2 R/W-0 WDTPS1 R/W-0 WDTPS0 R/W-0 SWDTEN bit 0
bit 0
TABLE 16-8:
Address 105h 81h
SUMMARY OF WATCHDOG TIMER REGISTERS
Name Bit 7 -- RBPU CPD Bit 6 -- INTEDG CP Bit 5 -- T0CS MCLRE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN T0SE PWRTE PSA WDTE PS2 FOSC2 PS1 FOSC1 PS0 FOSC0
WDTCON OPTION_REG
2007h(1) CONFIG
Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 16-1 for operation of all Configuration Word register bits.
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16.7 Power-Down Mode (Sleep)
The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: * * * * * WDT will be cleared but keeps running. PD bit in the Status register is cleared. TO bit is set. Oscillator driver is turned off. I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance). The following peripheral interrupts can wake the device from Sleep: 1. 2. 3. 4. 5. 6. 7. 8. 9. TMR1 Interrupt. Timer1 must be operating as an asynchronous counter. EUSART Receive Interrupt A/D conversion (when A/D clock source is RC) EEPROM write operation completion Comparator output changes state Interrupt-on-change External Interrupt from INT pin PLVD Interrupt LCD Interrupt (if running during Sleep)
For lowest current consumption in this mode, all I/O pins should be either at VDD or VSS, with no external circuitry drawing current from the I/O pin, and the comparators and CVREF should be disabled. I/O pins that are high-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level. Note: It should be noted that a Reset generated by a WDT time-out does not drive MCLR pin low.
Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction, then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. Note: If the global interrupts are disabled (GIE is cleared), but any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set, the device will immediately wake-up from Sleep. The SLEEP instruction is completely executed.
16.7.1
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the following events: 1. 2. 3. External Reset input on MCLR pin. Watchdog Timer wake-up (if WDT was enabled). Interrupt from RB0/INT/SEG0 pin, PORTB change or a peripheral interrupt.
The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up.
The first event will cause a device Reset. The two latter events are considered a continuation of program execution. The TO and PD bits in the Status register can be used to determine the cause of device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. TO bit is cleared if WDT wake-up occurred.
16.7.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from Sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will be cleared, the TO bit will be set and the PD bit will be cleared.
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Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
FIGURE 16-10:
OSC1(1) CLKO(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TOST(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Interrupt Latency (3) Processor in Sleep
PC Inst(PC) = Sleep Inst(PC - 1)
PC + 1 Inst(PC + 1) Sleep
PC + 2
PC + 2 Inst(PC + 2) Inst(PC + 1)
PC + 2
0004h Inst(0004h)
0005h Inst(0005h) Inst(0004h)
Dummy Cycle
Dummy Cycle
XT, HS or LP Oscillator mode assumed. TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes. GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line. CLKO is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
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16.8 Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSP for verification purposes. Note: The entire data EEPROM and Flash program memory will be erased when the code protection is turned off. See the "PIC16F917/916/914/913 Memory Programming Specification" (DS41244) for more information. A typical In-Circuit Serial Programming connection is shown in Figure 16-11.
FIGURE 16-11:
TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
To Normal Connections
External Connector Signals +5V 0V VPP CLK Data I/O
*
16.9
ID Locations
PIC16F917/916/ 914/913 VDD VSS RE3/MCLR/VPP RB6/ICSPCLK/ ICDCK/SEG14 RB7/ICSPDATA/ ICDDAT/SEG13
Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used.
16.10 In-Circuit Serial Programming
The PIC16F917/916/914/913 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for: * power * ground * programming voltage This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a Program/Verify mode by holding the RB7/ICSPDAT/ICDDAT/SEG13 and RB6/ICSPCLK/ICDCK/SEG14 pins low, while raising the MCLR (VPP) pin from VIL to VIHH. See "PIC16F917/916/914/913 Memory Programming Specification" (DS41244) for more information. RB7/ICSPDAT/ICDDAT/SEG13 becomes the programming data and RB6/ICSPCLK/ICDCK/SEG14 becomes the programming clock. Both RB7/ICSPDAT/ICDDAT/SEG13 and RB6/ICSPCLK/ICDCK/SEG14 are Schmitt Trigger inputs in this mode. After Reset, to place the device into Program/Verify mode, the Program Counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14 bits of program data are then supplied to or from the device, depending on whether the command was a load or a read. For complete details of serial programming, please refer to the "PIC16F917/916/914/913 Memory Programming Specification" (DS41244).
*
*
*
To Normal Connections * Isolation devices (as required)
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16.11 In-Circuit Debugger
The PIC16F917/916/914/913-ICD can be used in any of the package types. The device will be mounted on the target application board, which in turn has a 3 or 4 wire connection to the ICD tool. When the debug bit in the Configuration Word (CONFIG<12>) is programmed to a `0', the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB(R) ICD 2. When the microcontroller has this feature enabled, some of the resources are not available for general use. See Table 16-9 for more detail. Note: The user's application must have the circuitry required to support ICD functionality. Once the ICD circuitry is enabled, normal device pin functions on RB6/ICSPCLK/ICDCK/SEG14 and RB7/ICSPDAT/ICDDAT/SEG13 will not be usable. The ICD circuitry uses these pins for communication with the ICD2 external debugger. For more information, see "Using MPLAB(R) ICD 2" (DS51265), available on Microchip's web site (www.microchip.com). 16.11.1 ICD PINOUT The devices in the PIC16F91X family carry the circuitry for the In-Circuit Debugger on-chip and on existing device pins. This eliminates the need for a separate die or package for the ICD device. The pinout for the ICD device is the same as the devices (see Section 1.0 "Device Overview" for complete pinout and pin descriptions). Table 16-9 shows the location and function of the ICD related pins on the 28 and 40 pin devices.
TABLE 16-9:
PIC16F917/916/914/913-ICD PIN DESCRIPTIONS
Name Type TTL ST HV P P Pull-up -- -- -- -- -- Description In Circuit Debugger Bidirectional data In Circuit Debugger Bidirectional clock Programming voltage
Pin (PDIP) PIC16F914/917 40 39 1 11,32 12,31 PIC16F913/916 28 27 1 20 8,19 ICDDATA ICDCLK MCLR/VPP VDD VSS
Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, P = Power, HV = High Voltage
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17.0 INSTRUCTION SET SUMMARY
17.1
The PIC16F917/916/914/913 instruction set is highly orthogonal and is comprised of three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 17-1, while the various opcode fields are summarized in Table 17-1. Table 17-2 lists the instructions recognized by the MPASMTM assembler. A complete description of each instruction is also available in the "PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023). For byte-oriented instructions, `f' represents a file register designator and `d' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the W register. If `d' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, `b' represents a bit field designator, which selects the bit affected by the operation, while `f' represents the address of the file in which the bit is located. For literal and control operations, `k' represents an 8-bit or 11-bit constant, or literal value. One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a normal instruction execution time of 1 s. All instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. Note: To maintain upward compatibility with future products, do not use the OPTION and TRIS instructions.
READ-MODIFY-WRITE OPERATIONS
Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register. For example, a CLRF GPIO instruction will read GPIO, clear all the data bits, then write the result back to GPIO. This example would have the unintended result of clearing the condition that set the GPIF flag.
TABLE 17-1:
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. Program Counter Time-out bit Power-down bit
d
PC TO PD
All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit.
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FIGURE 17-1: GENERAL FORMAT FOR INSTRUCTIONS
0
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 8 7 k (literal)
0
0
0
k = 11-bit immediate value
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TABLE 17-2:
Mnemonic, Operands
PIC16F917/916/914/913 INSTRUCTION SET
14-Bit Opcode Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS LSb Status Affected Notes
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF
f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d
Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f
1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110
dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff
ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
C,DC,Z Z Z Z Z Z Z Z Z
1, 2 1, 2 2 1, 2 1, 2 1, 2, 3 1, 2 1, 2, 3 1, 2 1, 2
C C C,DC,Z Z
1, 2 1, 2 1, 2 1, 2 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b k k k k k k k k k Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff C,DC,Z Z TO,PD Z 1, 2 1, 2 3 3
LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk
TO,PD C,DC,Z Z
2: 3:
When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the PICmicro(R) Mid-Range MCU Family Reference Manual" (DS33023).
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17.2 Instruction Descriptions
Add Literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z The contents of the W register are added to the eight-bit literal `k' and the result is placed in the W register. Operation: Status Affected: Description: k BCF Syntax: Operands: Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None Bit `b' in register `f' is cleared. f,b ADDLW Syntax: Operands: Operation: Status Affected: Description:
ADDWF Syntax: Operands: Operation: Status Affected: Description:
Add W and f [ label ] ADDWF 0 f 127 d [0,1] (W) + (f) (destination) C, DC, Z Add the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
BSF Syntax: Operands: Operation: Status Affected: Description:
Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None Bit `b' in register `f' is set. f,b
ANDLW Syntax: Operands: Operation: Status Affected: Description:
AND Literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register. k
BTFSC Syntax: Operands: Operation: Status Affected: Description:
Bit Test, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None If bit `b' in register `f' is `1', the next instruction is executed. If bit `b' in register `f' is `0', the next instruction is discarded, and a NOP is executed instead, making this a two-cycle instruction.
ANDWF Syntax: Operands: Operation: Status Affected: Description:
AND W with f [ label ] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (destination) Z AND the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
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BTFSS Syntax: Operands: Operation: Status Affected: Description: Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None If bit `b' in register `f' is `0', the next instruction is executed. If bit `b' is `1', then the next instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. Status Affected: Description: CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
CALL Syntax: Operands: Operation:
Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction.
COMF Syntax: Operands: Operation: Status Affected: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. f,d
Status Affected: Description:
CLRF Syntax: Operands: Operation: Status Affected: Description:
Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z The contents of register `f' are cleared and the Z bit is set. f
DECF Syntax: Operands: Operation: Status Affected: Description:
Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'.
CLRW Syntax: Operands: Operation: Status Affected: Description:
Clear W [ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set.
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DECFSZ Syntax: Operands: Operation: Status Affected: Description: Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', then a NOP is executed instead, making it a two-cycle instruction. INCFSZ Syntax: Operands: Operation: Status Affected: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', a NOP is executed instead, making it a two-cycle instruction.
GOTO Syntax: Operands: Operation: Status Affected: Description:
Go to Address [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction.
IORLW Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are OR'ed with the eight-bit literal `k'. The result is placed in the W register.
INCF Syntax: Operands: Operation: Status Affected: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
IORWF Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
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MOVF Syntax: Operands: Operation: Status Affected: Encoding: Description: Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z
00 1000 dfff ffff
MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example:
Move W to f [ label ] (W) (f) None
00 0000 1fff ffff
MOVWF
f
0 f 127
The contents of register `f' is moved to a destination dependent upon the status of `d'. If `d' = 0, destination is W register. If `d' = 1, the destination is file register `f' itself. `d' = 1 is useful to test a file register since status flag Z is affected. 1 1
MOVF FSR,
Move data from W register to register `f'. 1 1
MOVWF OPTION
Words: Cycles: Example:
0
Before Instruction OPTION = W = After Instruction OPTION = W =
0xFF 0x4F 0x4F 0x4F
After Instruction W= value in FSR register Z=1
MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move Literal to W [ label ] k (W) None
11 00xx kkkk kkkk
NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example:
No Operation [ label ] None No operation None
00 0000 0xx0 0000
MOVLW k
NOP
0 k 255
The eight bit literal `k' is loaded into W register. The "don't cares" will assemble as `0's. 1 1
MOVLW 0x5A
No operation. 1 1
NOP
Words: Cycles: Example:
After Instruction W=
0x5A
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RETFIE Syntax: Operands: Operation: Status Affected: Encoding: Description: Return from Interrupt [ label ] None TOS PC, 1 GIE None
00 0000 0000 1001
RETLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None
11 01xx kkkk kkkk
RETFIE
Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. 1 2
RETFIE
The W register is loaded with the eight bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 1 2 CALL TABLE ;W contains table ;offset value * ;W now has table value * * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8
Words: Cycles: Example:
Words: Cycles: Example:
After Interrupt PC = GIE =
TOS 1
TABLE
RETURN Syntax: Operands: Operation: Status Affected: Description:
Return from Subroutine [ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN
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RLF Syntax: Operands: Operation: Status Affected: Encoding: Description: Rotate Left f through Carry [ label ] RLF f,d 0 f 127 d [0,1] See description below C
00 1101 dfff ffff
SLEEP Syntax: Operands: Operation: [ label ] SLEEP None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped.
Status Affected: Description:
The contents of register `f' are rotated one bit to the left through the Carry Flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'.
C Register f
Words: Cycles: Example:
1 1
RLF REG1,0
SUBLW Syntax: Operands:
= = = = = 1110 0110 0 1110 0110 1100 1100 1
Subtract W from Literal [ label ] SUBLW k 0 k 255 k - (W) (W) The W register is subtracted (2's complement method) from the eight-bit literal `k'. The result is placed in the W register.
Before Instruction
REG1 C
Operation: Description:
After Instruction
REG1 W C
Status Affected: C, DC, Z
RRF Syntax: Operands: Operation: Status Affected: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the right through the Carry Flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
C Register f
SUBWF Syntax: Operands: Operation: Description:
Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) (destination) Subtract (2's complement method) W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'.
Status Affected: C, DC, Z
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SWAPF Syntax: Operands: Operation: Status Affected: Description: Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in register `f'.
XORLW Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR Literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k (W) Z The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register.
XORWF Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR W with f [ label ] XORWF 0 f 127 d [0,1] (W) .XOR. (f) (destination) Z Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
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18.0 DEVELOPMENT SUPPORT
18.1
The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB ICE 4000 In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PICmicro MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
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18.2 MPASM Assembler 18.5
The MPASM Assembler is a full-featured, universal macro assembler for all PICmicro MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB ASM30 Assembler, Linker and Librarian
MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
18.6 18.3 MPLAB C18 and MPLAB C30 C Compilers
MPLAB SIM Software Simulator
The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 family of microcontrollers and dsPIC30F family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PICmicro MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, as well as internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool.
18.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
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18.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 18.9 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PICmicro MCUs and can be used to develop for these and other PICmicro MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers cost-effective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PICmicro devices.
The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application.
18.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PICmicro devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.
18.8
MPLAB ICE 4000 High-Performance In-Circuit Emulator
The MPLAB ICE 4000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for high-end PICmicro MCUs and dsPIC DSCs. Software control of the MPLAB ICE 4000 In-Circuit Emulator is provided by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 4000 is a premium emulator system, providing the features of MPLAB ICE 2000, but with increased emulation memory and high-speed performance for dsPIC30F and PIC18XXXX devices. Its advanced emulator features include complex triggering and timing, and up to 2 Mb of emulation memory. The MPLAB ICE 4000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.
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18.11 PICSTART Plus Development Programmer
The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PICmicro devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant.
18.12 Demonstration, Development and Evaluation Boards
A wide variety of demonstration, development and evaluation boards for various PICmicro MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart(R) battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest "Product Selector Guide" (DS00148) for the complete list of demonstration, development and evaluation kits.
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19.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings()
Ambient temperature under bias..........................................................................................................-40 to +125C Storage temperature ........................................................................................................................ -65C to +150C Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V Voltage on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) ............................................................................................................................... 800 mW Maximum current out of VSS pin ..................................................................................................................... 300 mA Maximum current into VDD pin ........................................................................................................................ 250 mA Input clamp current, IIK (VI < 0 or VI > VDD)................................................................................................................20 mA Output clamp current, IOK (Vo < 0 or Vo >VDD)..........................................................................................................20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Maximum current sourced by all ports (combined) ......................................................................................... 200 mA Maximum current sunk by by all ports (combined).......................................................................................... 200 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL). 2: PORTD and PORTE are not implemented in PIC16F913/916 devices. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Note:
Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin, rather than pulling this pin directly to VSS.
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FIGURE 19-1:
5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 8 10 12 16 20
PIC16F917/916/914/913 VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
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19.1 DC Characteristics: PIC16F917/916/914/913-I (Industrial) PIC16F917/916/914/913-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units Conditions FOSC < = 4 MHz: 2.0 3.0 4.5 VDR VPOR RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Brown-out Reset 1.5* -- -- -- -- -- VSS 5.5 5.5 5.5 -- -- V V V V V FOSC < = 10 MHz FOSC < = 20 MHz Device in Sleep mode See Section 16.3 "Power-on Reset" for details.
DC CHARACTERISTICS Param No. D001 D001C D001D D002 D003
Sym. VDD
Characteristic Supply Voltage
D004
SVDD
0.05 * --
--
--
V/ms See Section 16.3 "Power-on Reset" for details. V
D005
VBOR
2.1
--
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 221
PIC16F917/916/914/913
19.2 DC Characteristics: PIC16F917/916/914/913-I (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Conditions Device Characteristics Supply Current (IDD)(1, 2) Min. -- -- -- D011 -- -- -- D012 -- -- -- D013 -- -- -- D014 -- -- -- D015 -- -- -- D016 -- -- -- D017 -- -- -- D018 -- -- Typ 8 11 33 110 190 330 220 370 0.6 70 140 260 180 320 500 5 14 30 340 500 0.8 180 320 580 2.1 3.0 Max. TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Units VDD A A A A A A A A mA A A A A A A A A mA A A mA A A A mA mA 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 4.5 5.0 FOSC = 20 MHz HS Oscillator mode FOSC = 4 MHz EXTRC mode FOSC = 4 MHz INTOSC mode FOSC = 31 kHz INTOSC mode FOSC = 4 MHz EC Oscillator mode FOSC = 1 MHz EC Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode Note FOSC = 32 kHz LP Oscillator mode DC CHARACTERISTICS Param No. D010
Legend: TBD = To Be Determined Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
DS41250E-page 222
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
19.2 DC Characteristics: PIC16F917/916/914/913-I (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Conditions Device Characteristics Power-down Base Current (IPD)(4) Min. -- -- -- D021 -- -- -- D022 D023 -- -- -- -- -- D024 -- -- -- D025 -- -- -- D026 -- -- Typ 0.1 0.5 0.75 0.6 1.8 8.4 58 75 35 65 130 40 50.5 80 2.1 2.5 3.4 1.2 0.0022 Max. TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Units VDD A A A A A A A A A A A A A A A A A nA A 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 A/D Current T1OSC Current CVREF Current Comparator Current(3) BOR Current WDT Current Note WDT, BOR, Comparators, VREF and T1OSC disabled DC CHARACTERISTICS Param No. D020
Legend: TBD = To Be Determined Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 223
PIC16F917/916/914/913
19.3 DC Characteristics: PIC16F917/916/914/913-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended Conditions Device Characteristics
(1, 2)
DC CHARACTERISTICS Param No.
Min. -- -- --
Typ 8 11 33 110 190 330 220 370 0.6 70 140 260 180 320 500 5 14 30 340 500 0.8 180 320 580 2.1 3.0
Max. TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Units VDD A A A A A A A A mA A A A A A A A A mA A A mA A A A mA mA 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 4.5 5.0 FOSC = 20 MHz HS Oscillator mode FOSC = 4 MHz EXTRC mode FOSC = 4 MHz INTOSC mode FOSC = 31 kHz INTOSC mode FOSC = 4 MHz EC Oscillator mode FOSC = 1 MHz EC Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode Note FOSC = 32 kHz LP Oscillator mode
D010E Supply Current (IDD)
D011E
-- -- --
D012E
-- -- --
D013E
-- -- --
D014E
-- -- --
D015E
-- -- --
D016E
-- -- --
D017E
-- -- --
D018E
-- --
Legend: TBD = To Be Determined Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
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Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
19.3 DC Characteristics: PIC16F917/916/914/913-E (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended Conditions Device Characteristics Min. -- -- -- D021E -- -- -- D022E D023E -- -- -- -- -- D024E -- -- -- D025E -- -- -- D026E -- -- Typ 0.1 0.5 0.75 0.6 1.8 8.4 58 75 35 65 130 40 50.5 80 2.1 2.5 3.4 1.2 0.0022 Max. TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Units VDD A A A A A A A A A A A A A A A A A A A 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 A/D Current(3) T1OSC Current CVREF Current Comparator Current(3) BOR Current WDT Current Note WDT, BOR, Comparators, VREF and T1OSC disabled DC CHARACTERISTICS Param No.
D020E Power-down Base Current (IPD)(4)
Legend: TBD = To Be Determined Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 225
PIC16F917/916/914/913
19.4 DC Characteristics: PIC16F917/916/914/913-I (Industrial) PIC16F917/916/914/913-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units Conditions
DC CHARACTERISTICS Param Sym. No.
VIL D030 D030A D031 D032 D033 D033A D034 VIH D040 D040A D041 D042 D043 D043A D043B D044 D070 D060 D061 D063 VOL D080 D083 VOH D090 D092 IPUR IIL with Schmitt Trigger buffer MCLR, OSC1 (RC mode) OSC1 (XT and LP modes)(1) OSC1 (HS mode)(1) I2CTM mode Input High Voltage I/O port: with TTL buffer
Characteristic
Input Low Voltage I/O port: with TTL buffer
Vss Vss Vss VSS VSS VSS VSS
-- -- -- -- -- -- -- --
0.8 0.15 VDD 0.2 VDD 0.2 VDD 0.3 0.3 VDD 0.3VDD
V V V V V V V
4.5V VDD 5.5V Otherwise Entire range
Entire VDD Range
2.0 (0.25 VDD + 0.8) 0.8 VDD 0.8 VDD 1.6 0.7 VDD 0.9 VDD 0.7VDD 50* -- -- --
-- -- -- -- -- -- -- -- 250 0.1 0.1 0.1
VDD VDD VDD VDD VDD VDD VDD VDD 400* 1 5 5
V V V V V V V V A A
4.5V VDD 5.5V Otherwise Entire range (Note 1) (Note 1) Entire VDD Range VDD = 5.0V, VPIN = VSS VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VSS VPIN VDD, XT, HS and LP OSC configuration IOL = 8.5 mA, VDD = 4.5V (Ind.) IOL = 1.6 mA, VDD = 4.5V (Ind.) IOL = 1.2 mA, VDD = 4.5V (Ext.) IOH = -3.0 mA, VDD = 4.5V (Ind.) IOH = -1.3 mA, VDD = 4.5V (Ind.) IOH = -1.0 mA, VDD = 4.5V (Ext.)
with Schmitt Trigger buffer MCLR OSC1 (XT and LP modes) OSC1 (HS mode) OSC1 (RC mode) I2C mode PORTB Weak Pull-up Current Input Leakage I/O port MCLR(3) OSC1 Output Low Voltage I/O port OSC2/CLKO (RC mode) Output High Voltage I/O port OSC2/CLKO (RC mode) Current(2)
A A
-- --
-- --
0.6 0.6
V V
VDD - 0.7 VDD - 0.7
-- --
-- --
V V
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
DS41250E-page 226
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
19.4 DC Characteristics: PIC16F917/916/914/913-I (Industrial) PIC16F917/916/914/913-E (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units Conditions
DC CHARACTERISTICS Param Sym. No.
Characteristic Capacitive Loading Specs on Output Pins
D100
COS C2 CIO ED
OSC2 pin
--
--
15*
pF
In XT, HS and LP modes when external clock is used to drive OSC1
D101 D120 D121
All I/O pins Data EEPROM Memory Byte Endurance Byte Endurance
-- 100K 10K VMIN
-- 1M 100K --
50* -- -- 5.5
pF E/W -40C TA +85C E/W +85C TA +125C V Using EECON1 to read/write VMIN = Minimum operating voltage
D120A ED
VDRW VDD for Read/Write
D122 D123 D124
TDEW Erase/Write Cycle Time TRETD Characteristic Retention TREF Number of Total Erase/Write Cycles before Refresh(2) Program Flash Memory Cell Endurance Cell Endurance VDD for Read
-- 40 1M
5 -- 10M
6 -- --
ms Year Provided no other specifications are violated E/W -40C TA +85C
D130 D131 D132 D133 D134
EP VPR
10K 1K VMIN 4.5 -- 40
100K 10K -- -- 2 --
-- -- 5.5 5.5 2.5 --
E/W -40C TA +85C E/W +85C TA +125C V V ms Year Provided no other specifications are violated VMIN = Minimum operating voltage
D130A ED
VPEW VDD for Erase/Write TPEW Erase/Write cycle time TRETD Characteristic Retention
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 227
PIC16F917/916/914/913
19.5 Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F pp cc ck cs di do dt io mc S F H I L Fall High Invalid (High-impedance) Low P R V Z Period Rise Valid High-impedance CCP1 CLKO CS SDI SDO Data in I/O port MCLR osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR Frequency T Time Lowercase letters (pp) and their meanings:
Uppercase letters and their meanings:
FIGURE 19-2:
LOAD CONDITIONS
Load Condition 1 VDD/2 Load Condition 2
RL
Pin VSS
Legend: RL = 464 CL = 50 pF 15 pF
CL
Pin VSS
CL
for all pins for OSC2 output
DS41250E-page 228
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
19.6 AC Characteristics: PIC16F917/916/914/913 (Industrial, Extended)
EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
FIGURE 19-3:
OSC1 1 2 CLKO 3 3 4 4
TABLE 19-1:
EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. Sym. FOSC Characteristic External CLKI Frequency(1) Min. DC DC DC DC 5 -- DC 0.1 1 1 TOSC External CLKI Period(1) 27 50 50 250 27 -- 250 250 50 Typ -- -- -- -- -- 4 -- -- -- -- -- -- -- 250 -- -- -- Max. 37 4 20 20 37 -- 4 4 20 200 -- -- 10,000 1,000 Units kHz MHz MHz MHz kHz MHz MHz MHz MHz s ns ns ns s ns ns ns ns Conditions LP Oscillator mode XT Oscillator mode HS Oscillator mode EC Oscillator mode LP Oscillator mode INTOSC mode RC Oscillator mode XT Oscillator mode HS Oscillator mode LP Oscillator mode HS Oscillator mode EC Oscillator mode XT Oscillator mode LP Oscillator mode INTOSC mode RC Oscillator mode XT Oscillator mode HS Oscillator mode
Oscillator Frequency(1)
Oscillator Period(1)
200 TCY DC ns TCY = 4/FOSC 2* -- -- s LP oscillator, TOSC L/H duty cycle 20* -- -- ns HS oscillator, TOSC L/H duty cycle 100 * -- -- ns XT oscillator, TOSC L/H duty cycle 4 TosR, External CLKI Rise -- -- 50* ns LP oscillator TosF External CLKI Fall -- -- 25* ns XT oscillator -- -- 15* ns HS oscillator * These parameters are characterized but not tested. Data in `Typ' column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at `min' values with an external clock applied to OSC1 pin. When an external clock input is used, the `max' cycle time limit is `DC' (no clock) for all devices.
2 3
TCY TosL, TosH
Instruction Cycle Time(1) External CLKI (OSC1) High External CLKI Low
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 229
PIC16F917/916/914/913
TABLE 19-2: PRECISION INTERNAL OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. F10 Sym. Characteristic Freq. Min. Tolerance 1% 2% 5% -- -- -- Typ 8.00 8.00 8.00 Max. TBD TBD TBD Units Conditions
FOSC Internal Calibrated INTOSC Frequency(1)
MHz VDD and Temperature TBD MHz 2.5V VDD 5.5V 0C TA +85C MHz 2.0V VDD 5.5V -40C TA +85C (Ind.) -40C TA +125C (Ext.) s s s VDD = 2.0V, -40C to +85C VDD = 3.0V, -40C to +85C VDD = 5.0V, -40C to +85C
F14
ST
TIOSC Oscillator Wake-up from Sleep Start-up Time*
-- -- --
-- -- --
TBD TBD TBD
TBD TBD TBD
Legend: TBD = To Be Determined * These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 uF and 0.01 uF values in parallel are recommended.
DS41250E-page 230
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
FIGURE 19-4: CLKO AND I/O TIMING
Q4 OSC1 10 CLKO 13 14 I/O pin (Input) 17 I/O pin (Output) Old Value 20, 21 15 New Value 19 18 22 23 12 16 Q1 Q2 11 Q3
TABLE 19-3:
CLKO AND I/O TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. 10* 11* 12* 13* 14* 15* 16* 17* 18* 19* 20* 21* 22* 23* Sym. Characteristic Min. -- -- -- -- -- TOSC + 200 ns 0 -- -- TOSH2IOI OSC1 (Q2 cycle) to Port 3.0-5.5V Input Invalid (I/O in hold time) 2.0-5.5V 100 200 0 3.0-5.5V 2.0-5.5V TIOF TINP TRBP Port Output Fall Time INT Pin High or Low Time PORTA change INT High or Low Time 3.0-5.5V 2.0-5.5V -- -- -- -- 25 TCY Typ 75 75 35 35 -- -- -- 50 -- -- -- -- 10 -- 10 -- -- -- Max. 200 200 100 100 0.5 TCY + 20 -- -- 150* 300 -- -- -- 40 145 40 145 -- -- ns ns ns Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1)
TOSH2CKL OSC1 to CLOUT TOSH2CKH OSC1 to CLOUT TCKR TCKF TCKL2IOV TCKH2IOI CLKO Rise Time CLKO Fall Time CLKO to Port Out Valid Port In Hold after CLKO
TIOV2CKH Port In Valid before CLKO TOSH2IOV OSC1 (Q1 cycle) to Port Out Valid
TIOV2OSH Port Input Valid to OSC1 (I/O in setup time) TIOR Port Output Rise Time
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKO output is 4 x TOSC.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 231
PIC16F917/916/914/913
FIGURE 19-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset 34 I/O pins 32 30
31 34
FIGURE 19-6:
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD BVDD (Device in Brown-out Reset) (Device not in Brown-out Reset)
35
Reset (due to BOR)
64 ms Time-out(1)
Note 1:
64 ms delay only if PWRTE bit in the Configuration Word is programmed to `0'.
DS41250E-page 232
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(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
TABLE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. 30 31 32 33* 34 Sym. TMCL TWDT TOST TPWRT TIOZ Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O High-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Voltage Brown-out Reset Pulse Width Min. 2 11 10 10 -- 28* TBD -- Typ -- 18 17 17 1024 TOSC 64 TBD -- Max. Units -- 24 25 30 -- 132* TBD 2.0 s ms ms ms -- ms ms s Conditions VDD = 5V, -40C to +85C Extended temperature VDD = 5V, -40C to +85C Extended temperature TOSC = OSC1 period VDD = 5V, -40C to +85C Extended Temperature
BVDD 35 TBOR
2.025 100*
-- --
2.175 --
V s VDD BVDD (D005)
Legend: TBD = To Be Determined * These parameters are characterized but not tested. Data in `Typ' column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 19-7:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI 40 41
42
T1CKI 45 47 46 48
TMR0 or TMR1
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 233
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TABLE 19-5:
Param No. 40* 41* 42* Sym. TT0H TT0L TT0P
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler Min. 0.5 TCY + 20 10 0.5 TCY + 20 10 Greater of: 20 or TCY + 40 N Synchronous, No Prescaler Synchronous, with Prescaler Asynchronous 3.0-5.5V 2.0-5.5V 3.0-5.5V 2.0-5.5V 0.5 TCY + 20 15 25 30 50 0.5 TCY + 20 15 25 30 50 Greater of: 30 or TCY + 40 N 50 or TCY + 40 N 60 100 DC 2 TOSC* Typ -- -- -- -- -- Max. -- -- -- -- -- Units ns ns ns ns ns N = prescale value (2, 4, ..., 256) Conditions
45*
TT1H
T1CKI High Time
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1, 2, 4, 8)
46*
TT1L
T1CKI Low Time
Synchronous, No Prescaler Synchronous, with Prescaler Asynchronous 3.0-5.5V 2.0-5.5V 3.0-5.5V 2.0-5.5V
47*
TT1P
T1CKI Input Period
Synchronous
3.0-5.5V
2.0-5.5V Asynchronous FT1 48 3.0-5.5V 2.0-5.5V Timer1 oscillator input frequency range (oscillator enabled by setting bit T1OSCEN)
-- -- -- -- --
-- -- -- 37* 7 TOSC*
ns ns ns kHz --
TCKEZTMR1 Delay from external clock edge to timer increment *
These parameters are characterized but not tested. Data in `Typ' column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 19-8:
RC6/TX/CK SCK/SCL/SEG9
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
121 RC7/RX/DT/ SDI/SDA/SEG8 120 Note: Refer to Figure 19-2 for load conditions.
121
122
DS41250E-page 234
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
TABLE 19-6: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. 120 121 122 Symbol TCKH2DT V TCKRF TDTRF Characteristic SYNC XMIT (Master and Slave) Clock high to data-out valid Clock out rise time and fall time (Master mode) Data-out rise time and fall time 3.0-5.5V 2.0-5.5V 3.0-5.5V 2.0-5.5V 3.0-5.5V 2.0-5.5V Min. -- -- -- -- -- -- Max. 80 100 45 50 45 50 Units ns ns ns ns ns ns Conditions
FIGURE 19-9:
RC6/TX/CK SCK/SCL/SEG9 RC7/RX/DT/ SDI/SDA/SEG8
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
125
126 Note: Refer to Figure 19-2 for load conditions.
TABLE 19-7:
USART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. 125 126 Symbol Characteristic Min. Max. Units Conditions
TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK (DT hold time) TCKL2DTL Data-hold after CK (DT hold time)
10 15
-- --
ns ns
FIGURE 19-10:
CAPTURE/COMPARE/PWM TIMINGS
CCP1/CCP2 (Capture mode) 50 52 CCP1/CCP2 (Compare mode) 53 Note: Refer to Figure 19-2 for load conditions. 54 51
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 235
PIC16F917/916/914/913
TABLE 19-8: CAPTURE/COMPARE/PWM REQUIREMENTS
Min. No Prescaler With Prescaler No Prescaler With Prescaler 3.0-5.5V 2.0-5.5V 52* 53* 54* TCCP CCP1 input period TCCR CCP1 output fall time TCCF CCP1 output fall time 3.0-5.5V 2.0-5.5V 3.0-5.5V 2.0-5.5V 3.0-5.5V 2.0-5.5V 51* TCCH CCP1 input high time 0.5TCY + 5 10 20 0.5TCY + 5 10 20 3TCY + 40 N -- -- -- -- Typ Max. Units Conditions -- -- -- -- -- -- -- 10 25 10 25 -- -- -- -- -- -- -- 25 50 25 45 ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1,4 or 16) Param. Sym. Characteristic No. 50* TCCL CCP1 input low time
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested.
TABLE 19-9:
COMPARATOR SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Min. -- 0 +55* -- -- Typ. 5.0 -- -- 150 -- Max. 10 VDD - 1.5 -- 400* 10* Units mV V db ns s Comments
Comparator Specifications Sym. VOS VCM CMRR TRT Characteristics Input Offset Voltage Input Common Mode Voltage Common Mode Rejection Ratio Response Time(1)
TMC2COV Comparator Mode Change to Output Valid * Note 1:
These parameters are characterized but not tested. Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from VSS to VDD - 1.5V.
TABLE 19-10: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS
Voltage Reference Specifications Sym. Characteristics Resolution Absolute Accuracy Unit Resistor Value (R) Settling Time(1) * Note 1: Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Min. -- -- -- -- -- -- Typ. VDD/24* VDD/32 -- -- 2K* -- Max. -- -- 1/4* 1/2* -- 10* Units LSb LSb LSb LSb s Comments Low Range (VRR = 1) High Range (VRR = 0) Low Range (VRR = 1) High Range (VRR = 0)
These parameters are characterized but not tested. Settling time measured while VRR = 1 and VR<3:0> transitions from `0000' to `1111'.
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(c) 2005 Microchip Technology Inc.
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TABLE 19-11: PIC16F917/916/914/913 PLVD CHARACTERISTICS:
DC CHARACTERISTICS Sym. VPLVD PLVD Voltage Characteristic LVDL<2:0> = 000 TBD TBD TBD TBD TBD TBD TBD Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Operating Voltage VDD Range 2.0V-5.5V Min. TBD TBD TBD TBD TBD TBD TBD TBD Typ 1.9 2.0 2.1 2.2 2.3 4.0 4.2 4.5 Max. TBD TBD TBD TBD TBD TBD TBD TBD Units V V V V V V V V Conditions
Legend: TBD = To Be Determined Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 237
PIC16F917/916/914/913
FIGURE 19-11:
SS 70 SCK (CKP = 0) 71 72
SPITM MASTER MODE TIMING (CKE = 0, SMP = 0)
78
79
SCK (CKP = 1) 79 78
80 SDO MSb 75, 76 SDI MSb In 74 73 Note: Refer to Figure 19-2 for load conditions. bit 6 - - - -1
bit 6 - - - - - -1
LSb
LSb In
FIGURE 19-12:
SS
SPITM MASTER MODE TIMING (CKE = 1, SMP = 1)
81 SCK (CKP = 0) 71 73 SCK (CKP = 1) 80 78 72 79
SDO
MSb 75, 76
bit 6 - - - - - -1
LSb
SDI
MSb In 74
bit 6 - - - -1
LSb In
Note: Refer to Figure 19-2 for load conditions.
DS41250E-page 238
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
FIGURE 19-13:
SS 70 SCK (CKP = 0) 71 72 83
SPITM SLAVE MODE TIMING (CKE = 0)
78
79
SCK (CKP = 1) 79 78
80 SDO MSb 75, 76 SDI MSb In 74 73 Note: Refer to Figure 19-2 for load conditions. bit 6 - - - -1
bit 6 - - - - - -1
LSb 77 LSb In
FIGURE 19-14:
SPITM SLAVE MODE TIMING (CKE = 1)
82
SS
SCK (CKP = 0)
70 83 71 72
SCK (CKP = 1) 80
SDO
MSb 75, 76
bit 6 - - - - - -1
LSb 77
SDI
MSb In 74
bit 6 - - - -1
LSb In
Note: Refer to Figure 19-2 for load conditions.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 239
PIC16F917/916/914/913
TABLE 19-12: SPITM MODE REQUIREMENTS
Param No. 70* 71* 72* 73* 74* 75* 76* 77* 78* 79* 80* 81* 82* 83* Symbol Characteristic Min. TCY TCY + 20 TCY + 20 100 100 -- -- -- 10 -- -- -- 3.0-5.5V 2.0-5.5V -- -- Tcy -- 1.5TCY + 40 3.0-5.5V 2.0-5.5V Typ -- -- -- -- -- 10 25 10 -- 10 25 10 -- -- -- -- -- Max. Units Conditions -- -- -- -- -- 25 50 25 50 25 50 25 50 145 -- 50 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TSSL2SCH, SS to SCK or SCK input TSSL2SCL TSCH TSCL SCK input high time (Slave mode) SCK input low time (Slave mode)
TDIV2SCH, Setup time of SDI data input to SCK edge TDIV2SCL TSCH2DIL, TSCL2DIL TDOR TDOF TSSH2DOZ TSCR TSCF Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SS to SDO output high-impedance SCK output rise time (Master mode) SCK output fall time (Master mode) 3.0-5.5V 2.0-5.5V
TSCH2DOV, SDO data output valid after TSCL2DOV SCK edge
TDOV2SCH, SDO data output setup to SCK edge TDOV2SCL TSSL2DOV SDO data output valid after SS edge TSCH2SSH, SS after SCK edge TSCL2SSH
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 19-15:
I2CTM BUS START/STOP BITS TIMING
SCL 90 SDA
91 92
93
Start Condition Note: Refer to Figure 19-2 for load conditions.
Stop Condition
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(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
TABLE 19-13: I2CTM BUS START/STOP BITS REQUIREMENTS
Param No. 90* 91* 92* 93 * Symbol TSU:STA THD:STA TSU:STO Characteristic Start condition Setup time Start condition Hold time Stop condition Setup time THD:STO Stop condition Hold time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min. 4700 600 4000 600 4700 600 4000 600 Typ. Max. Units -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns Conditions Only relevant for Repeated Start condition After this period, the first clock pulse is generated
These parameters are characterized but not tested.
FIGURE 19-16:
I2CTM BUS DATA TIMING
103 100 101 102
SCL
90 91
106
107 92
SDA In 110 109 SDA Out Note: Refer to Figure 19-2 for load conditions. 109
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 241
PIC16F917/916/914/913
TABLE 19-14: I2CTM BUS DATA REQUIREMENTS
Param. No. 100* Symbol THIGH Characteristic Clock high time 100 kHz mode 400 kHz mode SSP Module 101* TLOW Clock low time 100 kHz mode 400 kHz mode SSP Module 102* TR SDA and SCL rise time SDA and SCL fall time Start condition setup time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min. 4.0 0.6 1.5TCY 4.7 1.3 1.5TCY -- 20 + 0.1CB -- 20 + 0.1CB 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- Max. -- -- -- -- -- -- 1000 300 300 300 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- 400 ns ns ns ns s s s s ns s ns ns s s ns ns s s pF Time the bus must be free before a new transmission can start (Note 1) (Note 2) CB is specified to be from 10-400 pF Only relevant for Repeated Start condition After this period the first clock pulse is generated CB is specified to be from 10-400 pF s s Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Units s s Conditions Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz
103*
TF
90* 91* 106* 107* 92* 109* 110*
TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF
Start condition hold 100 kHz mode time 400 kHz mode Data input hold time 100 kHz mode 400 kHz mode Data input setup time Stop condition setup time Output valid from clock Bus free time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode
CB * Note 1: 2:
Bus capacitive loading
These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released.
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(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
TABLE 19-15: PIC16F917/916/914/913 A/D CONVERTER CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. A01 A03 A04 A06 A07 A10 A20 A21 A22 A25 A30 Sym. NR EIL EDL EOFF EGN -- VREF Characteristic Resolution Integral Error Differential Error Offset Error Gain Error Monotonicity Reference Voltage (VREF+ - VREF-) Min. -- -- -- -- -- -- 2.5 VDD - 2.5V VSS - 0.3V VSS - 0.3V -- Typ -- -- -- -- -- assured(1) -- -- -- -- -- Max. 10 bits <1 <1 <1 <1 -- VDD VDD + 0.3V VREF+ -2V VREF+ +0.3V 10 Units bits LSb VREF = 5.0V LSb No missing codes to 10 bits VREF = 5.0V LSb VREF = 5.0V LSb VREF = 5.0V -- V V V V k VSS VAIN VREF+ Full 10-bit accuracy Conditions
VREF+ Reference Voltage High VREF- Reference Voltage Low VAIN ZAIN Analog Input Voltage Recommended Impedance of Analog Voltage Source VREF Input Current (2)
A50
IREF
--
--
5 150
A A
During VAIN acquisition. During A/D conversion cycle.
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: VREF+ current is from RA3/AN3/C1+/VREF+/SEG15 pin or VDD, whichever is selected as the VREF+ source. VREF- current is from RA2/AN2/C2+/VREF-/COM2 pin or VSS, whichever is selected as the VREF- source.
FIGURE 19-17:
PIC16F917/916/914/913 A/D CONVERSION TIMING (NORMAL MODE)
1 TCY 131 130
BSF ADCON0, GO 134 Q4 A/D CLK A/D Data ADRES ADIF GO Sample Note 1: 132 Sampling Stopped 9 8 OLD_DATA 7 6 3 2 1 0 (TOSC/2)(1)
NEW_DATA 1 TCY DONE
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
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Preliminary
DS41250E-page 243
PIC16F917/916/914/913
TABLE 19-16: PIC16F917/916/914/913 A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. 130 130 Sym. TAD TAD Characteristic A/D Clock Period(2) A/D Internal RC Oscillator Period Conversion Time (not including Acquisition Time)(1) Acquisition Time 5* Min. 1.6 3.0* 3.0* 2.0* 131 TCNV -- Typ -- -- 6.0 4.0 11 Max. -- -- 9.0* 6.0* -- Units s s s s TAD Conditions TOSC-based, VREF 3.0V TOSC-based, VREF full range ADCS<1:0> = 11 (RC mode) At VDD = 2.5V At VDD = 5.0V Set GO/DONE bit to new data in A/D Result register
132
TACQ
11.5 --
-- --
s s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 4.1 mV @ 4.096V) from the last sampled voltage (as stored on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
134
TGO
Q4 to A/D Clock Start
--
TOSC/2
--
--
* These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle. 2: See Table 12-1 for minimum conditions.
DS41250E-page 244
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
20.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
Graphs are not available at this time.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 245
PIC16F917/916/914/913
NOTES:
DS41250E-page 246
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
21.0
21.1
PACKAGING INFORMATION
Package Marking Information
28-Lead SPDIP
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC16F913-I/SP 0410017
40-Lead PDIP
XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC16F914-I/P 0410017
28-Lead QFN
Example
XXXXXXXX XXXXXXXX YYWWNNN
16F916 -I/ML 0410017
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
*
Standard PICmicro(R) device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 247
PIC16F917/916/914/913
Package Marking Information (Continued)
44-Lead QFN Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC16F914 -I/ML 0410017
28-Lead SOIC
XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC16F913-I/SO 0410017
28-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
Example PIC16F916-I/SS 0410017
44-Lead TQFP
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC16F917-I/PT 0310017
DS41250E-page 248
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
21.2 Package Details
The following sections give the technical details of the packages.
28-Lead Skinny Plastic Dual In-line (SP) - 300 mil Body (PDIP)
E1
D
2 n 1
E
A2 A L A1 B1 B p
c eB
Units Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom Dimension Limits n p A A2 A1 E E1 D L c B1 B eB MIN
INCHES* NOM 28 .100 .140 .125 .015 .300 .275 1.345 .125 .008 .040 .016 .320 5 5 .310 .285 1.365 .130 .012 .053 .019 .350 10 10 .325 .295 1.385 .135 .015 .065 .022 .430 15 15 .150 .130 .160 .135 MAX MIN
MILLIMETERS NOM 28 2.54 3.56 3.18 0.38 7.62 6.99 34.16 3.18 0.20 1.02 0.41 8.13 5 5 7.87 7.24 34.67 3.30 0.29 1.33 0.48 8.89 10 10 8.26 7.49 35.18 3.43 0.38 1.65 0.56 10.92 15 15 3.81 3.30 4.06 3.43 MAX
* Controlling Parameter Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-095
Drawing No. C04-070
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 249
PIC16F917/916/914/913
40-Lead Plastic Dual In-line (P) - 600 mil Body (PDIP)
E1
D
n E
2 1
A c eB Units Dimension Limits n p INCHES* NOM 40 .100 .175 .150 A1 B1 B p MILLIMETERS NOM 40 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 13.46 13.84 51.94 52.26 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.51 5 10 5 10
A2 L
MIN
MAX
MIN
MAX
Number of Pins Pitch Top to Seating Plane A .160 .190 Molded Package Thickness A2 .140 .160 Base to Seating Plane .015 A1 Shoulder to Shoulder Width E .595 .600 .625 Molded Package Width E1 .530 .545 .560 Overall Length D 2.045 2.058 2.065 Tip to Seating Plane L .120 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .030 .050 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .620 .650 .680 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-016
4.83 4.06 15.88 14.22 52.45 3.43 0.38 1.78 0.56 17.27 15 15
DS41250E-page 250
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body (QFN) - With 0.55 mm Contact Length (Saw Singulated)
E
EXPOSED METAL PAD
E2
e
D
D2
2 1 n
b
TOP VIEW
OPTIONAL INDEX AREA
ALTERNATE INDEX INDICATORS
SEE DETAIL
L
BOTTOM VIEW
A1 A
DETAIL ALTERNATE PAD OUTLINE
Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Contact Width Contact Length
Units Dimension Limits n e A A1 A3 E E2 D D2 b L
MIN
.031 .000 .232 .140 .232 .140 .009 .020
INCHES NOM 28 .026 BSC .035 .001 .008 REF .236 .146 .236 .146 .011 .024
MAX
MIN
.039 .002 .240 .152 .240 .152 .013 .028
0.80 0.00 5.90 3.55 5.90 3.55 0.23 0.50
MILLIMETERS* NOM 28 0.65 BSC 0.90 0.02 0.20 REF 6.00 3.70 6.00 3.70 0.28 0.60
MAX
1.00 0.05 6.10 3.85 6.10 3.85 0.33 0.70
*Controlling Parameter Notes: JEDEC equivalent: MO-220
Drawing No. C04-105 Revised 05-24-04
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 251
PIC16F917/916/914/913
44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)
DS41250E-page 252
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
28-Lead Plastic Small Outline (SO) - Wide, 300 mil Body (SOIC)
E E1 p
D
B n h 45 c A Units Dimension Limits n p A A2 A1 E E1 D h L c B L A1 INCHES* NOM 28 .050 .099 .091 .008 .407 .295 .704 .020 .033 4 .011 .017 12 12 MILLIMETERS NOM 28 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.32 7.49 17.65 17.87 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.42 0 12 0 12 A2 2 1
MIN
MAX
MIN
MAX
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
.093 .088 .004 .394 .288 .695 .010 .016 0 .009 .014 0 0
.104 .094 .012 .420 .299 .712 .029 .050 8 .013 .020 15 15
2.64 2.39 0.30 10.67 7.59 18.08 0.74 1.27 8 0.33 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 253
PIC16F917/916/914/913
28-Lead Plastic Shrink Small Outline (SS) - 209 mil Body, 5.30 mm (SSOP)
E E1 p
D
B n 2 1
A c
A2 f L A1
Number of Pins Pitch Overall Height A .079 Molded Package Thickness A2 .065 .073 Standoff A1 .002 Overall Width E .295 .323 Molded Package Width E1 .009 .220 Overall Length D .390 .413 Foot Length L .022 .037 c Lead Thickness .004 .010 f Foot Angle 0 8 Lead Width B .009 .015 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-150
Drawing No. C04-073
Units Dimension Limits n p
MIN
INCHES NOM 28 .026 .069 .307 .209 .402 .030 4 -
MAX
MIN
MILLIMETERS* NOM 28 0.65 1.65 1.75 0.05 7.49 7.80 5.00 5.30 9.90 10.20 0.55 0.75 0.09 0 4 0.22 -
MAX
2.0 1.85 8.20 5.60 10.50 0.95 0.25 8 0.38
DS41250E-page 254
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E E1 #leads=n1 p
D1
D
B n
2 1
CH x 45 A
c
L A1 (F) Units Dimension Limits n p n1 A A2 A1 L (F) E D E1 D1 c B CH INCHES NOM 44 .031 11 .043 .039 .004 .024 .039 3.5 .472 .472 .394 .394 .006 .015 .035 10 10 MILLIMETERS* NOM 44 0.80 11 1.00 1.10 0.95 1.00 0.05 0.10 0.45 0.60 1.00 0 3.5 11.75 12.00 11.75 12.00 9.90 10.00 9.90 10.00 0.09 0.15 0.30 0.38 0.64 0.89 5 10 5 10 A2
MIN
MAX
MIN
MAX
Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff Foot Length Footprint (Reference) Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Pin 1 Corner Chamfer Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
.039 .037 .002 .018 0 .463 .463 .390 .390 .004 .012 .025 5 5
.047 .041 .006 .030 7 .482 .482 .398 .398 .008 .017 .045 15 15
1.20 1.05 0.15 0.75 7 12.25 12.25 10.10 10.10 0.20 0.44 1.14 15 15
Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-076
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 255
PIC16F917/916/914/913
NOTES:
DS41250E-page 256
Preliminary
(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
APPENDIX A:
Revision A
This is a new data sheet.
DATA SHEET REVISION HISTORY
APPENDIX B:
MIGRATING FROM OTHER PICmicro(R) DEVICES
This discusses some of the issues in migrating from other PICmicro devices to the PIC16F917/916/914/913 family of devices.
Revision B
Updated Peripheral Features. Page 2, Table: Corrected I/O numbers. Figure 8-3: Revised Comparator I/O operating modes. Register 9-1, Table: Corrected max. number of pixels.
B.1
PIC16F676 to PIC16F917/916/914/ 913
FEATURE COMPARISON
PIC16F676 20 MHz 1K 64 10-bit 128 1/1 8 Y RB0/1/2/4/5 RB0/1/2/3 /4/5 1 N N N 4 MHz N PIC16F917/ 916/914/913 20 MHz 8K 352 10-bit 256 2/1 8 Y RB<7:0> RB<7:4> 2 Y Y Y 32 kHz 8 MHz Y
TABLE B-1:
Feature
Revision C
Correction to Pin Description Table. Correction to IPD base and T1OSC. Max Operating Speed Max Program Memory (Words) Max SRAM (Bytes) A/D Resolution Data EEPROM (bytes) Timers (8/16-bit) Oscillator Modes Brown-out Reset Internal Pull-ups Interrupt-on-change Comparator USART Extended WDT Software Control Option of WDT/BOR INTOSC Frequencies Clock Switching
Revision D
Revised references 31.25 kHz to 31 kHz. Revised Standby Current to 100 nA. Revised 9.1: internal RC oscillator to internal LF oscillator.
Revision E
Removed "Advance Information" from Section 19.0 Electrical Specifications. Removed 28-Lead Plastic Quad Flat No Lead Package (ML) (QFN-S) package.
(c) 2005 Microchip Technology Inc.
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APPENDIX C: CONVERSION CONSIDERATIONS
Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in Table C-1.
TABLE C-1:
Pins Timers Interrupts Communication Frequency Voltage A/D CCP Comparator
CONVERSION CONSIDERATIONS
PIC16F917/916/914/913 28/40 3 11 or 12 USART, SSP (SPITM, I2CTM Slave) 20 MHz 2.0V-5.5V 10-bit, 7 conversion clock selects 2 2 Yes 4K, 8K EPROM PIC16F87X 28/40 3 13 or 14 PSP, USART, SSP (SPI, I2C Master/Slave) 20 MHz 2.2V-5.5V 10-bit, 4 conversion clock selects 2 -- -- 4K, 8K Flash (Erase/Write on single-word) 192, 368 bytes 128, 256 bytes Segmented, starting at end of program memory On/Off PIC16F87XA 28/40 3 14 or 15 PSP, USART, SSP (SPI, I2C Master/Slave) 20 MHz 2.0V-5.5V 10-bit, 7 conversion clock selects 2 2 Yes 4K, 8K Flash (Erase/Write on four-word blocks) 192, 368 bytes 128, 256 bytes On/Off Segmented, starting at beginning of program memory -- In-Circuit Debugger, Low-Voltage Programming
Characteristic
Comparator Voltage Reference Program Memory
RAM EEPROM Data Code Protection Program Memory Write Protection LCD Module Other
256, 352 bytes 256 bytes On/Off --
16, 24 segment drivers, 4 commons In-Circuit Debugger, Low-Voltage Programming
-- In-Circuit Debugger, Low-Voltage Programming
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INDEX
A
A/D Acquisition Requirements ......................................... 149 Analog Port Pins ....................................................... 144 Associated Registers ................................................ 151 Block Diagram........................................................... 143 Calculating Acquisition Time..................................... 149 Channel Selection..................................................... 144 Configuration and Operation..................................... 144 Configuring................................................................ 148 Configuring Interrupt ................................................. 148 Conversion (TAD) Cycles .......................................... 145 Conversion Clock...................................................... 144 Effects of Reset......................................................... 151 Internal Sampling Switch (RSS) Impedance.............. 149 Operation During Sleep ............................................ 150 Output Format........................................................... 145 Reference Voltage (VREF)......................................... 144 Source Impedance.................................................... 149 Specifications............................................................ 244 Starting a Conversion ............................................... 145 TAD vs. Operating Frequencies................................. 144 Absolute Maximum Ratings .............................................. 219 AC Characteristics Industrial and Extended ............................................ 229 Load Conditions ........................................................ 228 ACK pulse ......................................................................... 169 ADCON0 Register............................................................. 146 ADCON1 Register............................................................. 147 Addressable Universal Synchronous Asynchronous Receiver Transmitter. See USART Analog Input Connections ................................................... 94 Analog-to-Digital Converter Module. See A/D ANSEL Register ................................................................ 146 Assembler MPASM Assembler................................................... 216 Asynchronous Reception Associated Registers ........................................ 135, 137 Asynchronous Transmission Associated Registers ................................................ 133 PWM Mode............................................................... 181 RA0 Pin ...................................................................... 33 RA1 Pin ...................................................................... 34 RA2 Pin ...................................................................... 35 RA3 Pin ...................................................................... 36 RA4 Pin ...................................................................... 37 RA5 Pin ...................................................................... 38 RA6 Pin ...................................................................... 39 RA7 Pin ...................................................................... 40 RB Pins....................................................................... 45 RB4 Pin ...................................................................... 46 RB5 Pin ...................................................................... 47 RB6 Pin ...................................................................... 48 RB7 Pin ...................................................................... 49 RC0 Pin ...................................................................... 52 RC1 Pin ...................................................................... 53 RC2 Pin ...................................................................... 53 RC3 Pin ...................................................................... 54 RC4 Pin ...................................................................... 55 RC5 Pin ...................................................................... 56 RC6 Pin ...................................................................... 57 RC7 Pin ...................................................................... 58 RD Pins ...................................................................... 63 RD0 Pin ...................................................................... 62 RD1 Pin ...................................................................... 62 RD2 Pin ...................................................................... 63 RE Pins....................................................................... 66 Resonator Operation .................................................. 74 SSP (I2C Mode)........................................................ 169 SSP (SPI Mode) ....................................................... 162 System Clock.............................................................. 69 Timer1 ........................................................................ 85 Timer2 ........................................................................ 91 TMR0/WDT Prescaler ................................................ 81 USART Receive ............................................... 135, 136 USART Transmit ...................................................... 132 Watchdog Timer (WDT)............................................ 199 BRGH bit .......................................................................... 129 Brown-out Reset (BOR).................................................... 189 Associated Registers................................................ 190 Calibration ................................................................ 189 Specifications ........................................................... 233 Timing and Characteristics ....................................... 232
B
Baud Rate Generator Associated Registers ................................................ 129 BF bit................................................................................. 160 Block Diagrams A/D ............................................................................ 143 Analog Input Model ............................................. 94, 150 Capture Mode ........................................................... 179 Comparator 1 .............................................................. 96 Comparator 2 .............................................................. 96 Comparator Modes ..................................................... 95 Comparator Voltage Reference (CVREF) .................... 98 Compare Mode ......................................................... 180 Fail-Safe Clock Monitor (FSCM) ................................. 79 In-Circuit Serial Programming Connections.............. 203 Interrupt Logic ........................................................... 196 LCD Clock Generation .............................................. 108 LCD Driver Module ................................................... 102 LCD Resistor Ladder Connection ............................. 106 MCLR Circuit............................................................. 188 On-Chip Reset Circuit ............................................... 187 PIC16F913/916............................................................. 8 PIC16F914/917............................................................. 9
C
C Compilers MPLAB C18.............................................................. 216 MPLAB C30.............................................................. 216 Capture/Compare/PWM (CCP) ........................................ 177 Associated Registers Capture, Compare and Timer1......................... 182 PWM and Timer2.............................................. 183 Capture Mode........................................................... 179 Block Diagram .................................................. 179 CCP1CON Register.......................................... 178 CCP1IF............................................................. 179 Prescaler .......................................................... 179 CCP Timer Resources.............................................. 177 Compare Special Trigger Output of CCP1 ....................... 180 Special Trigger Output of CCP2 ....................... 180 Compare Mode......................................................... 180 Block Diagram .................................................. 180 Software Interrupt Mode ................................... 180
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Special Event Trigger........................................ 180 Interaction of Two CCP Modules (table) ................... 177 PWM Mode ............................................................... 180 Block Diagram................................................... 181 Duty Cycle......................................................... 181 Example Frequencies/Resolutions (table) ........ 182 PWM Period...................................................... 181 Special Event Trigger and A/D Conversions............. 180 CCP. See Capture/Compare/PWM CCP1CON Register .................................................... 64, 178 CCPR1H Register ............................................................. 177 CCPR1L Register.............................................................. 177 CCPxM0 bit ....................................................................... 178 CCPxM1 bit ....................................................................... 178 CCPxM2 bit ....................................................................... 178 CCPxM3 bit ....................................................................... 178 CCPxX bit.......................................................................... 178 CCPxY bit.......................................................................... 178 CKE bit .............................................................................. 160 CKP bit .............................................................................. 161 CMCON0 Register .............................................................. 93 CMCON1 Register .............................................................. 97 Code Examples A/D Conversion ......................................................... 148 Assigning Prescaler to Timer0 .................................... 83 Assigning Prescaler to WDT ....................................... 83 Call of a Subroutine in Page 1 from Page 0................ 29 Indirect Addressing ..................................................... 30 Initializing PORTA ....................................................... 31 Initializing PORTB ....................................................... 41 Initializing PORTC....................................................... 51 Initializing PORTD....................................................... 60 Initializing PORTE ....................................................... 65 Loading the SSPBUF (SSPSR) Register .................. 163 Saving Status and W Registers in RAM ................... 198 Code Protection ................................................................ 203 Comparator Module ............................................................ 93 Comparator Voltage Reference (CVREF) Associated Registers ................................................ 100 Effects of a Reset........................................................ 99 Response Time ........................................................... 99 Comparator Voltage Reference (CVREF) ............................ 98 Accuracy/Error ............................................................ 98 Configuring.................................................................. 98 Specifications ............................................................ 236 Comparators Associated Registers ................................................ 100 C2OUT as T1 Gate ............................................... 86, 97 Configurations ............................................................. 95 Effects of a Reset........................................................ 99 Interrupts ..................................................................... 97 Operation .................................................................... 94 Operation During Sleep .............................................. 99 Outputs ....................................................................... 97 Response Time ........................................................... 99 Specifications ............................................................ 236 Synchronizing C2OUT w/ Timer1 ............................... 97 CONFIG Register.............................................................. 186 Configuration Bits.............................................................. 186 Conversion Considerations ............................................... 258 CPU Features ................................................................... 185 Customer Change Notification Service ............................. 267 Customer Notification Service........................................... 267 Customer Support ............................................................. 267
D
D/A bit ............................................................................... 160 Data EEPROM Memory.................................................... 153 Associated Registers ................................................ 158 Reading .................................................................... 156 Writing ...................................................................... 156 Data Memory ...................................................................... 14 Data/Address bit (D/A)...................................................... 160 DC Characteristics Extended and Industrial ............................................ 226 Industrial and Extended ............................................ 221 Development Support ....................................................... 215 Device Overview................................................................... 7
E
EEADRH Registers................................................... 153, 154 EEADRL Registers ................................................... 153, 154 EECON1 Register..................................................... 153, 155 EECON2 Register............................................................. 153 EEDATH Register............................................................. 154 EEDATL Register ............................................................. 154 Electrical Specifications .................................................... 219 Enhanced Capture/Compare/PWM (ECCP) Enhanced PWM Mode TMR2 to PR2 Match ........................................... 90 Errata .................................................................................... 5
F
Fail-Safe Clock Monitor ...................................................... 79 Fail-Safe Condition Clearing....................................... 80 Reset and Wake-up from Sleep.................................. 80 Firmware Instructions ....................................................... 205 Flash Program Memory .................................................... 153 Fuses. See Configuration Bits
G
General Purpose Register File ........................................... 14
I
I/O Ports.............................................................................. 31 I2C Mode Addressing................................................................ 170 Associated Registers ................................................ 176 Master Mode............................................................. 175 Mode Selection ......................................................... 169 Multi-Master Mode .................................................... 175 Operation .................................................................. 169 Reception ................................................................. 171 Slave Mode SCL and SDA pins............................................ 169 Transmission ............................................................ 173 ID Locations...................................................................... 203 In-Circuit Debugger........................................................... 204 In-Circuit Serial Programming (ICSP)............................... 203 Indirect Addressing, INDF and FSR Registers ................... 30 Instruction Format............................................................. 206 Instruction Set................................................................... 205 ADDLW..................................................................... 208 ADDWF..................................................................... 208 ANDLW..................................................................... 208 ANDWF..................................................................... 208 BCF .......................................................................... 208 BSF........................................................................... 208 BTFSC ...................................................................... 209 BTFSS ...................................................................... 208
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CALL ......................................................................... 209 CLRF......................................................................... 209 CLRW ....................................................................... 209 CLRWDT................................................................... 209 COMF ....................................................................... 209 DECF ........................................................................ 209 DECFSZ.................................................................... 210 GOTO ....................................................................... 210 INCF.......................................................................... 210 INCFSZ ..................................................................... 210 IORLW ...................................................................... 210 IORWF ...................................................................... 210 MOVF........................................................................ 211 MOVLW .................................................................... 211 MOVWF .................................................................... 211 NOP .......................................................................... 211 RETFIE ..................................................................... 212 RETLW ..................................................................... 212 RETURN ................................................................... 212 RLF ........................................................................... 213 RRF........................................................................... 213 SLEEP ...................................................................... 213 SUBLW ..................................................................... 213 SUBWF ..................................................................... 213 SWAPF ..................................................................... 214 XORLW..................................................................... 214 XORWF..................................................................... 214 Summary Table......................................................... 207 INTCON Register ................................................................ 23 Inter-Integrated Circuit (I2C). See I2C Mode Internal Oscillator Block INTOSC Specifications.................................................... 230 Internal Sampling Switch (Rss) Impedance ...................... 149 Internet Address................................................................ 267 Interrupt Sources USART Receive/Transmit Complete ........................ 127 Interrupts ........................................................................... 195 A/D ............................................................................ 148 Associated Registers ................................................ 197 Comparators ............................................................... 97 Context Saving.......................................................... 198 Interrupt-on-change .................................................... 41 PORTB Interrupt-on-Change .................................... 196 RB0/INT/SEG0.......................................................... 196 TMR0 ........................................................................ 196 TMR1 .......................................................................... 86 TMR2 to PR2 Match ................................................... 91 TMR2 to PR2 Match (PWM) ....................................... 90 INTOSC Specifications ..................................................... 230 IOCB Register ..................................................................... 42 Pixel Control ............................................................. 107 Prescaler .................................................................. 106 Segment Enables ..................................................... 107 Waveform Generation .............................................. 110 LCDCON Register ............................................................ 101 LCDDATA Register........................................................... 101 LCDPS Register ............................................................... 101 LP Bits ...................................................................... 106 LCDSE Register ............................................................... 101 Liquid Crystal Display (LCD) Driver .................................. 101 Load Conditions................................................................ 228
M
MCLR ............................................................................... 188 Internal...................................................................... 188 Memory Organization ......................................................... 13 Data ............................................................................ 14 Program...................................................................... 13 Microchip Internet Web Site.............................................. 267 Migrating from other PICmicro Devices ............................ 257 MPLAB ASM30 Assembler, Linker, Librarian ................... 216 MPLAB ICD 2 In-Circuit Debugger ................................... 217 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator.................................................... 217 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator.................................................... 217 MPLAB Integrated Development Environment Software.. 215 MPLAB PM3 Device Programmer .................................... 217 MPLINK Object Linker/MPLIB Object Librarian ................ 216
O
OPCODE Field Descriptions............................................. 205 OPTION_REG Register................................................ 22, 82 OSCCON Register.............................................................. 70 Oscillator Associated Registers.................................................. 80 Oscillator Configurations..................................................... 69 Oscillator Delay Examples.......................................... 72 Special Cases............................................................. 71 Oscillator Specifications.................................................... 229 Oscillator Start-up Timer (OST) Specifications ........................................................... 233 Oscillator Switching Fail-Safe Clock Monitor .............................................. 79 Two-Speed Clock Start-up ......................................... 78 OSCTUNE Register............................................................ 76
P
P (Stop) bit........................................................................ 160 Packaging ......................................................................... 247 Marking............................................................. 247, 248 PDIP Details ............................................................. 249 SOIC Details............................................................. 253 TSSOP Details ......................................................... 253 Paging, Program Memory................................................... 29 PCL and PCLATH............................................................... 29 Computed GOTO ....................................................... 29 Stack........................................................................... 29 PCON Register ................................................................. 190 PICSTART Plus Development Programmer..................... 218 PIE1 Register ..................................................................... 24 PIE2 Register ..................................................................... 25 Pin Diagram PIC16F913/916, 28-pin ................................................ 3 PIC16F914/917, 40-pin ................................................ 2 PIC16F914/917, 44-pin ................................................ 4
L
LCD Associated Registers ................................................ 124 Bias Types ................................................................ 106 Clock Source Selection............................................. 106 Configuring the Module............................................. 124 Frame Frequency...................................................... 107 Interrupts................................................................... 121 LCDCON Register .................................................... 101 LCDDATA Register................................................... 101 LCDPS Register........................................................ 101 LCDSE Register........................................................ 101 Multiplex Types ......................................................... 107 Operation During Sleep ............................................ 122
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Pinout Description ............................................................... 10 PIR1 Register...................................................................... 26 PIR2 Register...................................................................... 27 PORTA Associated Registers .................................................. 40 Pin Descriptions and Diagrams................................... 33 RA0 ............................................................................. 33 RA1 ............................................................................. 34 RA2 ............................................................................. 35 RA3 ............................................................................. 36 RA4 ............................................................................. 37 RA5 ............................................................................. 38 RA6 ............................................................................. 39 RA7 ............................................................................. 40 Registers ..................................................................... 31 Specifications ............................................................ 231 PORTA Register ................................................................. 32 PORTB Additional Pin Functions ............................................. 41 Weak Pull-up....................................................... 41 Associated Registers .................................................. 50 Interrupt-on-change .................................................... 41 Pin Descriptions and Diagrams................................... 44 RB0 ............................................................................. 44 RB1 ............................................................................. 44 RB2 ............................................................................. 44 RB3 ............................................................................. 44 RB4 ............................................................................. 46 RB5 ............................................................................. 47 RB6 ............................................................................. 48 RB7 ............................................................................. 49 Registers ..................................................................... 41 PORTB Register ................................................................. 42 PORTC Associated Registers .................................................. 59 Pin Descriptions and Diagrams................................... 52 RC0 ............................................................................. 52 RC1 ............................................................................. 52 RC2 ............................................................................. 52 RC3 ............................................................................. 54 RC4 ............................................................................. 55 RC5 ............................................................................. 56 RC6 ............................................................................. 57 RC6/TX/CK/SCK/SCL/SEG9 Pin .............................. 128 RC7 ............................................................................. 58 RC7/RX/DT Pin ......................................................... 129 RC7/RX/DT/SDI/SDA/SEG8 Pin ............................... 128 Registers ..................................................................... 51 Specifications ............................................................ 231 TRISC Register ......................................................... 127 PORTC Register ................................................................. 51 PORTD Associated Registers .................................................. 64 Pin Descriptions and Diagrams................................... 61 RD0 ............................................................................. 61 RD1 ............................................................................. 61 RD2 ............................................................................. 61 RD3 ............................................................................. 61 RD4 ............................................................................. 61 RD5 ............................................................................. 61 RD6 ............................................................................. 61 RD7 ............................................................................. 61 Registers ..................................................................... 60 PORTD Register ................................................................. 60 PORTE Associated Registers .................................................. 67 Pin Descriptions and Diagrams .................................. 66 RE0............................................................................. 66 RE1............................................................................. 66 RE2............................................................................. 66 RE3............................................................................. 66 Registers .................................................................... 65 PORTE Register ................................................................. 65 Power-Down Mode (Sleep)............................................... 201 Power-on Reset ................................................................ 188 Power-up Timer (PWRT) .................................................. 188 Specifications ........................................................... 233 Precision Internal Oscillator Parameters .......................... 230 Prescaler Shared WDT/Timer0................................................... 83 Switching Prescaler Assignment ................................ 83 Product Identification System ........................................... 269 Program Memory ................................................................ 13 Map and Stack (PIC16F913/914) ............................... 13 Map and Stack (PIC16F916/917) ............................... 13 Paging ........................................................................ 29 Programmable Low-Voltage Detect (PLVD) Module ........ 125 Programming, Device Instructions .................................... 205 Pulse Width Modulation.SeeCapture/Compare/PWM, PWM Mode.
R
R/W bit .............................................................................. 160 RCSTA Register ADDEN Bit ................................................................ 128 CREN Bit .................................................................. 128 FERR Bit................................................................... 128 OERR Bit .................................................................. 128 RX9 Bit ..................................................................... 128 RX9D Bit ................................................................... 128 SPEN Bit........................................................... 127, 128 SREN Bit .................................................................. 128 Reader Response............................................................. 268 Read-Modify-Write Operations ......................................... 205 Receive Overflow Indicator bit (SSPOV) .......................... 161 Registers ADCON0 (A/D Control 0).......................................... 146 ADCON1 (A/D Control 1).......................................... 147 ANSEL (Analog Select) ............................................ 146 CCP1CON (CCP Control 2)...................................... 178 CCP2CON (CCP Control 1)...................................... 178 CMCON0 (Comparator Control 0) .............................. 93 CMCON1 (Comparator Control 1) .............................. 97 CONFIG (Configuration Word) ................................. 186 EEADRH (EEPROM Address).................................. 154 EEADRL (EEPROM Address) .................................. 154 EECON1 (EEPROM Control 1) ................................ 155 EEDATH (EEPROM Data)........................................ 154 EEDATL (EEPROM Data) ........................................ 154 INTCON (Interrupt Control)......................................... 23 IOCB (PORTB Interrupt-on-change)........................... 42 LCDCON (LCD Control) ........................................... 103 LCDDATAx (LCD Datax) .......................................... 105 LCDPS (LCD Prescaler Select) ................................ 104 LCDSEn (LCD Segment).......................................... 105 LVDCON (Low-Voltage Detect Control) ................... 125 OPTION_REG ...................................................... 22, 82 OSCCON (Oscillator Control) ..................................... 70 OSCTUNE .................................................................. 76 PCON (Power Control) ............................................. 190 PIE1 (Peripheral Interrupt Enable 1)........................... 24
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PIE2 (Peripheral Interrupt Enable 2)........................... 25 PIR1 (Peripheral Interrupt Register 1) ........................ 26 PIR2 (Peripheral Interrupt Register 2) ........................ 27 PORTA........................................................................ 32 PORTB........................................................................ 42 PORTC ....................................................................... 51 PORTD ....................................................................... 60 PORTE........................................................................ 65 RCSTA (Receive Status and Control)....................... 128 Reset Values............................................................. 192 Reset Values (Special Registers) ............................. 194 Special Function Register Map PIC16F913/916................................................... 15 PIC16F914/917................................................... 16 Special Register Summary Bank 0................................................................. 17 Bank 1................................................................. 18 Bank 2................................................................. 19 Bank 3................................................................. 20 SSPCON (Sync Serial Port Control) Register........... 161 SSPSTAT (Sync Serial Port Status) Register........... 160 Status.......................................................................... 21 T1CON (Timer1 Control)............................................. 87 T2CON (Timer2 Control)............................................. 90 TRISA (PORTA Tri-state) ........................................... 32 TRISB (PORTB Tri-state) ........................................... 42 TRISC (PORTC Tri-state) ........................................... 51 TRISD (PORTD Tri-state) ........................................... 60 TRISE (PORTE Tri-state) ........................................... 65 TXSTA (Transmit Status and Control) ...................... 127 VRCON (Voltage Reference Control) ....................... 100 WDTCON (Watchdog Timer Control) ....................... 200 WPUB (Weak Pull-up PORTB) ................................... 43 Reset................................................................................. 187 Revision History ................................................................ 257 SPI Master Mode...................................................... 165 SPI Slave Mode........................................................ 166 SSPBUF ................................................................... 165 SSPSR ..................................................................... 165 SSPEN bit......................................................................... 161 SSPM bits ......................................................................... 161 SSPOV bit ........................................................................ 161 Status Register ................................................................... 21 Synchronous Master Reception Associated Registers................................................ 140 Synchronous Master Transmission Associated Registers................................................ 139 Synchronous Serial Port Enable bit (SSPEN) .................. 161 Synchronous Serial Port Mode Select bits (SSPM).......... 161 Synchronous Serial Port. See SSP Synchronous Slave Reception Associated Registers................................................ 142 Synchronous Slave Transmission Associated Registers................................................ 142
T
T1CON Register ................................................................. 87 Time-out Sequence .......................................................... 190 Timer0 Associated Registers.................................................. 83 External Clock ............................................................ 82 External Clock Requirements ................................... 234 Interrupt ...................................................................... 81 Operation.................................................................... 81 T0CKI ......................................................................... 82 Timer0 Module.................................................................... 81 Timer1 Associated Registers.................................................. 89 Asynchronous Counter Mode ..................................... 88 Reading and Writing ........................................... 88 External Clock Requirements ................................... 234 Interrupt ...................................................................... 86 Modes of Operations .................................................. 86 Operation During Sleep .............................................. 89 Prescaler .................................................................... 86 Resetting of Timer1 Registers .................................... 89 Resetting Timer1 Using a CCP Trigger Output .......... 88 Timer1 Gate Inverting Gate ..................................................... 86 Selecting Source .......................................... 86, 97 Synchronizing C2OUT w/ Timer1 ....................... 97 TMR1H Register......................................................... 85 TMR1L Register ......................................................... 85 Timer1 Module with Gate Control ....................................... 85 Timer2 ................................................................................ 90 Associated registers ................................................... 91 Operation.................................................................... 90 Postscaler................................................................... 90 PR2 Register .............................................................. 90 Prescaler .................................................................... 90 TMR2 Output .............................................................. 91 TMR2 Register ........................................................... 90 TMR2 to PR2 Match Interrupt............................... 90, 91 Timing Diagrams A/D Conversion ........................................................ 243 Asynchronous Master Transmission ........................ 132 Asynchronous Master Transmission (Back to Back) 132 Asynchronous Reception.......................................... 135 Asynchronous Reception with Address Byte First .... 137 Asynchronous Reception with Address Detect......... 137 Brown-out Reset (BOR)............................................ 232
S
S (Start) bit ........................................................................ 160 SCI. See USART Serial Communication Interface. See USART. Slave Select Synchronization ........................................... 166 SMP bit ............................................................................. 160 Software Simulator (MPLAB SIM)..................................... 216 Special Function Registers ................................................. 14 SPI Mode .................................................................. 159, 166 Associated Registers ................................................ 168 Bus Mode Compatibility ............................................ 168 Effects of a Reset...................................................... 168 Enabling SPI I/O ....................................................... 164 Master Mode ............................................................. 165 Master/Slave Connection.......................................... 164 Serial Clock (SCK pin) .............................................. 159 Serial Data In (SDI pin) ............................................. 159 Serial Data Out (SDO pin) ........................................ 159 Slave Select .............................................................. 159 Slave Select Synchronization ................................... 166 Sleep Operation ........................................................ 168 SPI Clock .................................................................. 165 Typical Connection ................................................... 164 SSP Overview SPI Master/Slave Connection ................................... 164 SSP I2C Operation ............................................................ 169 Slave Mode ............................................................... 169 SSP Module Clock Synchronization and the CKP Bit.................... 175
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Brown-out Reset Situations ...................................... 189 Capture/Compare/PWM............................................ 235 CLKO and I/O ........................................................... 231 Clock Synchronization .............................................. 176 Comparator Output ..................................................... 94 External Clock ........................................................... 229 Fail-Safe Clock Monitor (FSCM) ................................. 80 I2C Bus Data ............................................................. 241 I2C Bus Start/Stop Bits.............................................. 240 I2C Reception (7-bit Address) ................................... 171 I2C Slave Mode (Transmission, 10-bit Address) ....... 174 I2C Slave Mode with SEN = 0 (Reception, 10-bit Address).................................................. 172 I2C Transmission (7-bit Address) .............................. 173 INT Pin Interrupt........................................................ 197 LCD Interrupt Timing in Quarter-Duty Cycle Drive.... 121 LCD Sleep Entry/Exit when SLPEN = 1 or CS = 00 . 123 Reset, WDT, OST and Power-up Timer ................... 232 Slave Synchronization .............................................. 166 SPI Master Mode (CKE = 1, SMP = 1) ..................... 238 SPI Mode (Master Mode) .......................................... 165 SPI Mode (Slave Mode with CKE = 0) ...................... 167 SPI Mode (Slave Mode with CKE = 1) ...................... 167 SPI Slave Mode (CKE = 0) ....................................... 239 SPI Slave Mode (CKE = 1) ....................................... 239 Synchronous Reception (Master Mode, SREN) ....... 141 Synchronous Transmission....................................... 139 Synchronous Transmission (Through TXEN) ........... 139 Time-out Sequence Case 1............................................................... 191 Case 2............................................................... 191 Case 3............................................................... 191 Timer0 and Timer1 External Clock ........................... 233 Timer1 Incrementing Edge.......................................... 86 Two Speed Start-up .................................................... 79 Type-A in 1/2 Mux, 1/2 Bias Drive ............................ 111 Type-A in 1/2 Mux, 1/3 Bias Drive ............................ 113 Type-A in 1/3 Mux, 1/2 Bias Drive ............................ 115 Type-A in 1/3 Mux, 1/3 Bias Drive ............................ 117 Type-A in 1/4 Mux, 1/3 Bias Drive ............................ 119 Type-A/Type-B in Static Drive................................... 110 Type-B in 1/2 Mux, 1/2 Bias Drive ............................ 112 Type-B in 1/2 Mux, 1/3 Bias Drive ............................ 114 Type-B in 1/3 Mux, 1/2 Bias Drive ............................ 116 Type-B in 1/3 Mux, 1/3 Bias Drive ............................ 118 Type-B in 1/4 Mux, 1/3 Bias Drive ............................ 120 USART Synchronous Receive (Master/Slave) ......... 235 USART Synchronous Transmission (Master/Slave) . 234 Wake-up from Interrupt ............................................. 202 Timing Parameter Symbology........................................... 228 Timing Requirements I2C Bus Data ............................................................. 242 I2C Bus Start/Stop Bits ............................................. 241 SPI Mode .................................................................. 240 TMR1H Register ................................................................. 85 TMR1L Register .................................................................. 85 TRISA Registers ..................................................................... 31 TRISA Register ................................................................... 32 TRISB Registers ..................................................................... 41 TRISB Register ................................................................... 42 TRISC Registers ..................................................................... 51 TRISC Register ................................................................... 51 TRISD Registers .................................................................... 60 TRISD Register................................................................... 60 TRISE Registers .................................................................... 65 TRISE Register................................................................... 65 Two-Speed Clock Start-up Mode........................................ 78 TXSTA Register BRGH Bit .................................................................. 127 CSRC Bit .................................................................. 127 SYNC Bit .................................................................. 127 TRMT Bit................................................................... 127 TX9 Bit ...................................................................... 127 TX9D Bit ................................................................... 127 TXEN Bit ................................................................... 127
U
UA..................................................................................... 160 Update Address bit, UA .................................................... 160 USART.............................................................................. 127 Address Detect Enable (ADDEN Bit)........................ 128 Asynchronous Mode ................................................. 131 Asynchronous Receive (9-bit Mode)......................... 136 Asynchronous Receive with Address Detect. See Asynchronous Receive (9-bit Mode). Asynchronous Receiver............................................ 134 Asynchronous Reception.......................................... 134 Asynchronous Transmitter........................................ 131 Baud Rate Generator (BRG) .................................... 129 Baud Rate Formula .......................................... 129 Baud Rates, Asynchronous Mode (BRGH = 0) 130 Baud Rates, Asynchronous Mode (BRGH = 1) 130 High Baud Rate Select (BRGH Bit) .................. 127 Sampling........................................................... 129 Clock Source Select (CSRC Bit)............................... 127 Continuous Receive Enable (CREN Bit)................... 128 Framing Error (FERR Bit) ......................................... 128 Mode Select (SYNC Bit) ........................................... 127 Overrun Error (OERR Bit)......................................... 128 Receive Data, 9th Bit (RX9D Bit).............................. 128 Receive Enable, 9-bit (RX9 Bit) ................................ 128 Serial Port Enable (SPEN Bit) .......................... 127, 128 Single Receive Enable (SREN Bit) ........................... 128 Synchronous Master Mode....................................... 138 Requirements, Synchronous Receive .............. 235 Requirements, Synchronous Transmission...... 235 Timing Diagram, Synchronous Receive ........... 235 Timing Diagram, Synchronous Transmission... 234 Synchronous Master Reception................................ 140 Synchronous Master Transmission .......................... 138 Synchronous Slave Mode......................................... 141 Synchronous Slave Reception.................................. 142 Synchronous Slave Transmit.................................... 141 Transmit Data, 9th Bit (TX9D) .................................. 127 Transmit Enable (TXEN Bit) ..................................... 127 Transmit Enable, Nine-bit (TX9 Bit) .......................... 127 Transmit Shift Register Status (TRMT Bit) ............... 127
V
Voltage Reference. See Comparator Voltage Reference (CVREF) VRCON Register .............................................................. 100
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W
Wake-up Using Interrupts ................................................. 201 Watchdog Timer (WDT) .................................................... 199 Associated Registers ................................................ 200 Clock Source............................................................. 199 Modes ....................................................................... 199 Period........................................................................ 199 Specifications............................................................ 233 WCOL bit .......................................................................... 161 WDTCON Register ........................................................... 200 WPUB Register ................................................................... 43 Write Collision Detect bit (WCOL)..................................... 161 WWW Address.................................................................. 267 WWW, On-Line Support ....................................................... 5
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PIC16F917/916/914/913
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
(c) 2005 Microchip Technology Inc.
Preliminary
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PIC16F917/916/914/913
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS41250E FAX: (______) _________ - _________
Device: PIC16F917/916/914/913 Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
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(c) 2005 Microchip Technology Inc.
PIC16F917/916/914/913
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) PIC16F913-E/SP 301 = Extended Temp., skinny PDIP package, 20 MHz, QTP pattern #301 PIC16F913-I/SO = Industrial Temp., SOIC package, 20 MHz
b) Device PIC16F917/916/914/913(1), PIC16F917/916/914/913T(2)
Temperature Range
I E
= =
-40C to +85C -40C to +125C
Package
ML P PT SO SP SS
= = = = = =
Micro Lead Frame (QFN) Plastic DIP TQFP (Thin Quad Flatpack) SOIC Skinny Plastic DIP SSOP Note 1: F = Standard Voltage Range LF = Wide Voltage Range T = In tape and reel.
Pattern
3-Digit Pattern Code for QTP (blank otherwise)
2:
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type.
(c) 2005 Microchip Technology Inc.
Preliminary
DS41250E-page 269
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8676-6200 Fax: 86-28-8676-6599 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256
ASIA/PACIFIC
India - Bangalore Tel: 91-80-2229-0061 Fax: 91-80-2229-0062 India - New Delhi Tel: 91-11-5160-8631 Fax: 91-11-5160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 604-646-8870 Fax: 604-646-5086 Philippines - Manila Tel: 632-634-9065 Fax: 632-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Weis Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-352-30-52 Fax: 34-91-352-11-47 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
08/24/05
DS41250E-page 270
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(c) 2005 Microchip Technology Inc.

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